m3s012an.v

mentor UART IP verilog源码 以通过验证.

// FIFO Element Cell
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.100

// This module provides the FIFO elements
// for the M16550a UART.
// The module uses a read strobe as well as a write strobe 
// to allow substitution of a dual port RAM for the whole FIFO. 

// Revision history:
// V1.100  - 15 June 1999
//           Changed constant from 8'h0 to 8'h00 to clear lint warning (ECN 1242)
// V1.000  - 26 September 1996
//           Original

module m3s012an (
  CLK, IP_D, IpSel, OpSel, NVWR, NVRD, OP_D
  );

input       CLK;
input [7:0] IP_D;
input       IpSel, OpSel, NVWR, NVRD;

output [7:0] OP_D;

reg [7:0] Data, OP_D;

always @(posedge CLK)
  if (IpSel & ~NVWR)
    Data <= IP_D;

always @(OpSel or NVRD or Data)
  if (OpSel & ~NVRD)
    OP_D = Data;
  else
    OP_D = 8'h00;

endmodule