m3s005an.v

mentor UART IP verilog源码 以通过验证.

// Baud Rate Generator
// Copyright Mentor Graphics Corporation and Licensors 1999
// V10.600

// This module provides the baud rate generator
// for the M16550a UART.
//
// Revision history:
// V10.6 - 15 June 1999
//           Changed constant from 16'h01 to 16'h0001 to clear lint warning (ECN 1242)
// V10.5 - 13 May 1999
//         Uses single input clock
//         A counter enable signal allows a prescaler to be used

// V10.4 - ECN 1228 Modified to fix fifo polled bug - 26/3/99
//	   ECN 1222 Baud rate clock re-written to fix glitch in Baud output 5/2/99

// V10.3 - Changed to suit M16550a ( was M16c450 ) - 26/6/98
//	   Added RCLK_BAUD option and changed generation of TCLK and RCLK SYNCH pulses
//	 - Removed TCLK input and use BAUd output instead
//	 _ Added RCLK_BAUD input to allow Rx baud selection

// V10.2 - Removed unnecessary pipelining ECN 919 - 15/5/98
//	 - Added fast clock input fclock. 
//	 - Feed in tclk and rclk to the BRG and synchronise them to fclk.
//	 - to produce BEN for transmit and receive engines
//	 - Added new MRB reset to remove simulation errors
// V10.1 - Changed baud generator to mimic real device - 30/7/97. 
// V10.0 - Recoded from the original schematic design - 27 Nov 1996

module m3s005an (
  CLK, MR, RCLK, RCLK_BAUD, BRGE, NWR, ADD0B, ADD1B, DI,
  DIV, BAUD, TxClkEnab, RxClkEnab
  );

input       CLK, MR, RCLK, RCLK_BAUD, BRGE, NWR, ADD0B, ADD1B;
input [7:0] DI;

output [15:0] DIV;
output        BAUD, TxClkEnab, RxClkEnab;

reg       BAUD, TxClkEnab, RxClkEnab;
reg[15:0] DIV, BRG;
reg       DDIV, BrLoad, BRG_One, SyncRClk, DelRClk;
reg [1:0] SDDIV;


// Baud Rate generator registers

// CPU Channel timing domain
always @(posedge NWR or posedge MR)
  if (MR)
    DIV <= 16'h0001;
  else
  begin
    if (ADD0B)
      DIV <= {DIV[15:8],DI[7:0]};
    else if (ADD1B)
      DIV <= {DI[7:0],DIV[7:0]};
  end

// Generation of the counter load bit, counter is loaded anytime
// there is a write to either the LSB, or the MSB of the divisor
// register
always @(posedge NWR or posedge MR) 
  if (MR)
    DDIV <= 1'b0;
  else if (ADD0B | ADD1B)
    DDIV <= ~SDDIV[1];      // Delta bit

// Clock Timing domain
always @(posedge CLK or posedge MR) 
  if (MR)
    SDDIV <= 2'b01;
  else 
    SDDIV <= {SDDIV[0],DDIV};

always @(SDDIV)
  BrLoad = SDDIV[0] ^ SDDIV[1];


// Baud Rate Counter
always @(posedge CLK or posedge MR)
  if (MR)
    BRG <= 1;
  else if (BrLoad | BRG_One)
    BRG <= DIV;
  else if (BRGE)
    BRG <= BRG - 1;

// Detect BRG = 1
always @(BRG or BRGE)
  BRG_One = (BRG == 16'h0001) & BRGE;

// Generate BAUD output
always @(posedge CLK or posedge MR)
  if (MR)
    BAUD <= 1;
  else
  begin
    if (BRG_One | BrLoad)
      BAUD <= 1;
    else if (BRG[15:1] == 15'h0001)
      BAUD <= 0;
  end

// Generate transmitter enable
always @(posedge CLK or posedge MR)
  if (MR)
    TxClkEnab <= 1;
  else
    TxClkEnab <= BRG_One;

// Synchronise RCLK for edge detection
always @(posedge CLK or posedge MR)
  if (MR)
  begin
    SyncRClk <= 0;
    DelRClk <= 0;
  end
  else
  begin
    SyncRClk <= RCLK;
    DelRClk <= SyncRClk;
  end

// Generate receiver enable
always @(RCLK_BAUD or TxClkEnab or SyncRClk or DelRClk)
  if (RCLK_BAUD)
    RxClkEnab = TxClkEnab;
  else
    RxClkEnab = SyncRClk & ~DelRClk;

endmodule