m16550a.v

mentor UART IP verilog源码 以通过验证.

// M16550a UART
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.9

// This is the top level module. It instantiates and connects
// up the lower levels.
// 
// Revision history:
// V1.900 - 29 September 1999
//          Remove signal THold1 from this module as superflous (ECN 1267)
// V1.8   - 15 June 1999
//          Changed ports for m3s004 due to input removal (ECN 1242)
// V1.7   - 13 May 1999
//        - Single input clock used.
//        - BRGE input added to allow an external prescaler to be added.
//        - Error FIFO can be replaced by a RAM block
// V1.6   - Added RX_CLOCK and TX_CLOCK inputs to clock
//	  - Tx and Rx engines in different clock modes
//	  - Changed M3s005 block to utilise version from M16C450
// 	  - RCLK re-routed to Baud Rate Generator
//	  - Tx and Rx now clocked with FCLK and controlled by BRG
//	  - Parameterised to allow for fast or normal FCLK
// V1.5   - Added Fast Clock FCLK which clocks the whole design apart from the Baud
//	    Rate Generator. D. Kingston 4/3/98
// V1.4   - TX now clocked with CLK (not TCLK) and a BEN signal from BAUD Generator.
//	    TCLK removed.
//	    Removed REMPTY from m3s004.
//	    Removed FIFOE from m3s011.
//          RX Engine now clocked with CLK and BEN signal from BAUD Generator or from
//          RCLK which is internally synchronised to CLK inside RX Engine; RCLK_BAUD is 
//          used to switch between the two states.
//          Signals IDMA, IFIFOE, DELTA_TRST, RCLK_BAUD added.
//          Added RD into m3s02an.v  10/11/97
//	    Added RD intp m3s008an.v 10/11/97
//	    Added RD intp m3s011an.v 10/11/97
// V1.3   - TSRE and TEMPT added to m3s004an inputs  23/9/97
// V1.2   - TCLK and RCK added, BEN changed to BAUD -28/7/97 
// V1.1   - ROP_A, RIP_A, TOP_A, and TIP_A reduced to 4-bits
// V1.0   - Created 26/9/96

module m16550a (
  CLK, RCLK, MR,
  A, DI, NCE, NRD, RD, NWR,
  NDCD, NRI, NDSR, NCTS, SIN, RCLK_BAUD, BRGE,
  DA, IRQ, NDVL, NOUT2, NOUT1, NRTS, NDTR, SOUT, BAUD,
  TXRDY, RXRDY
  );

input       CLK, RCLK, MR;
input [2:0] A;
input [7:0] DI;
input       NCE, NRD, RD, NWR, NDCD, NRI, NDSR, NCTS, SIN, RCLK_BAUD, BRGE;

output [7:0] DA;
output       IRQ, NDVL, NOUT2, NOUT1, NRTS, NDTR, SOUT, BAUD;
output       TXRDY, RXRDY;

wire        TXRDY, RXRDY;
wire        TXD, THRe, PEN, WLS0, WLS1, STB, EPS, SP, SB;
wire  [7:0] RXD, TFD, RFD, RX;
wire        DR, FE, OE, PE, BI, ADD0, ADD5;
wire        ADD1, ADD2, ADD4, ADD6, ADD0B, ADD1B;
wire  [3:0] IER, IIR;
wire [15:0] DIV;
wire        TxClkEnab, RxClkEnab;
wire        LOOP1, RTS, DTR, TSRE, DDCD, TERI, DDSR, DCTS, BRKTD;
wire  [3:0] TIP_A, TOP_A;
wire  [3:0] RIP_A, ROP_A;
wire  [2:0] OP_ED;
wire        TEmpt, TFull, FIFOE;
wire        FRE, PTE, FBRK, ERF, RTO, FOE, FERF;
wire        RFull, REmpt, RRST, DMA, RTL, RTM;
wire        LoadTxBuff, CharEn;
wire        RHold1, RxAboveTrig;
wire        NTRD, NTWR, NRWR, NRRD;
wire        RxBlank, IFIFOE, Delta_TRST;


// Instantiate the modules and connect them up - no logic at this top
// level of the design

// Transmit block
m3s001an U1(
  CLK, MR, TxClkEnab, NWR, ADD0, TFD, DI, 
  PEN, WLS0, WLS1, STB, EPS, SP, FIFOE, TEmpt,
  TXD, THRe, TSRE, LoadTxBuff
  );


// Receive block
m3s002an U2(
  CLK, MR, RxClkEnab, NRD, RD, ADD0, ADD5,
  DA[4], DA[3], DA[2], DA[1],
  PEN, WLS0, WLS1, STB, EPS, SP,
  SIN, LOOP1, BRKTD, RFD,
  FOE, OP_ED[2], OP_ED[1], OP_ED[0], FERF, FIFOE, REmpt, RRST,
  RXD, RX, CharEn, DR, FE, OE, PE, BI,
  ERF, RTO, FRE, PTE, FBRK, RxBlank
  );


// Address decode block 
m3s003an U3(
  CLK, MR, NCE, NRD, RD, NWR, 
  A, DI, IIR, IER, DIV, RXD,
  LOOP1, OUT1, OUT2, RTS, DTR, TSRE, THRe,
  BI, FE, PE, OE, DR, ERF, DCD, RI,
  DSR, CTS, DDCD, TERI, DDSR, DCTS, RxBlank,
  PEN, WLS0, WLS1, STB, EPS, SP, SB, NDVL,
  DA, ADD0, ADD1, ADD2, ADD4, ADD5, ADD6, ADD0B, ADD1B,
  FIFOE, IFIFOE, DMA, IDMA, RTL, RTM
  );


// Interrupt Priority encoder 
m3s004an U4 (
  CLK         ,
  MR          , 
  NWR         ,
  NRD         , 
  RD          , 
  ADD0        , 
  ADD1        , 
  ADD2        ,
  DI[3:0]     , 
  DR          , 
  BI          , 
  FE          ,
  PE          ,
  OE          , 
  RTO         ,
  DDCD        , 
  TERI        , 
  DDSR        , 
  DCTS        , 
  THRe        ,
  DA[1]       , 
  DA[2]       , 
  LoadTxBuff  , 
  FIFOE       , 
  IFIFOE      ,
  DMA         , 
  IDMA        , 
  TFull       , 
  RHold1      ,
  RxAboveTrig ,
  TSRE        , 
  TEmpt       , 
  Delta_TRST  , 
  RRST        ,
  IRQ         , 
  IIR         , 
  IER         , 
  TXRDY       , 
  RXRDY       
  );


// Baud Rate generation block
m3s005an U5 (
  CLK, MR, RCLK, RCLK_BAUD, BRGE, NWR, ADD0B, ADD1B, DI,
  DIV, BAUD, TxClkEnab, RxClkEnab
  );


// Modem interface block
m3s006an U6 (
  CLK, MR, NRD, NWR, ADD4, ADD6, DI[4:0], DA[3:0],
  NDCD, TXD, SB, NRI, NDSR, NCTS,
  NOUT1, NOUT2, NRTS, NDTR, BRKTD, SOUT, LOOP1,
  OUT1, OUT2, DCD, RI, DSR, CTS, RTS, DTR,
  DDCD, DCTS, DDSR, TERI
  );


// Tx FIFO controller
m3s007an U7 (
  CLK, MR, NWR, ADD0, ADD2, LoadTxBuff,
  DI[2], DI[0], FIFOE,
  TOP_A, TIP_A, TEmpt, TFull, NTWR, NTRD, Delta_TRST
  );


// Rx FIFO controller
m3s008an U8 (
  CLK, MR, NWR, NRD, RD,
  ADD0, ADD2, ADD5,
  CharEn, DI[1], DI[0], FIFOE, RTM, RTL,
  ROP_A, RIP_A, REmpt, RFull, RxAboveTrig,
  RHold1, RRST, FOE, NRWR, NRRD
  );


// Tx FIFO
m3s009an U9 (
  NWR, DI, TIP_A, TOP_A, NTWR, NTRD, TFD
  );


// Rx FIFO
m3s010an U10 (
  CLK, RX, RIP_A, ROP_A, NRWR, NRRD, RFD
  );


// Error fifo
m3s011an U11 (
  CLK, MR, RD, NRD, ADD0, ADD5, RIP_A, ROP_A,
  PTE, FRE, FBRK, CharEn, RRST, REmpt, RFull,
  OP_ED, FERF
  );

endmodule