m3s008an.v

mentor UART IP verilog源码 以通过验证.

// Receive FIFO Controller
// Copyright Mentor Graphics Corporation and Licensors 1999
// V1.400

// This module provides the receive FIFO control
// for the M16550a UART.

// Revision history:
// V1.400 - 15 June 1999
//          Removal of unused variables RSR2, RxAboveTrigDel (ECN 1242)
//          Changed constant from 2'b0 to 2'b00 to clear lint warning (ECN 1242)
// V1.300 - 12 May 1999
//          Signals renamed, FIFO trigger levels decoded
// V1.2   - Updated OP_A with posedge of RD instead of posedge of NRD,
//	    14/11/97
// V1.1   - OP_A and IP_A reduced to 4-bits in the port list
// V1.0   - Created 26/9/96


module m3s008an (
  CLK, MR, NWR, NRD, RD,
  ADD0, ADD2, ADD5,
  CharEn, DI1, DI0, FIFOE, RTM, RTL,
  ROP_A, RIP_A, REmpt, RFull, RxAboveTrig,
  RHold1, RRST, FOE, NVWR, NVRD
  );

input CLK, MR, NWR, NRD, RD;
input ADD0, ADD2, ADD5;
input CharEn, DI1, DI0, FIFOE, RTM, RTL;

output [3:0] ROP_A, RIP_A;
output       REmpt, RFull;     
output       RxAboveTrig;
output       RHold1, RRST, FOE;
output       NVRD, NVWR;


reg [3:0] ROP_A, RIP_A;
reg [4:0] OP_A, IP_A, ROffset;
reg [1:0] RSR;
reg       DRRST, RHold1;
reg       RxTrig1, RxTrig2, RxTrig3, RxTrig4;
reg       RxAboveTrig, Trigger;
reg       DOE, DOER, FOE, RRST, NVWR, NVRD;
reg       REmpt, RFull;

// Generate reset for Rx FIFO counter using bit 1 in FCR & MR
always @(posedge NWR or posedge MR)
begin
  if (MR)
    DRRST <= 1'b0;   
  else if (ADD2 & DI1 & DI0)
    DRRST <= ~RSR[1];
end

always @(posedge CLK or posedge MR)
begin
  if (MR)
    RSR[1:0] <= 2'b00;
  else 
  begin
    RSR[0] <= DRRST;
    RSR[1] <= RSR[0];
  end
end

// Holds FIFOs in reset when disabled
always @(DRRST or RSR or FIFOE)
  RRST = (DRRST ^ RSR[1]) | ~FIFOE;

// Prevent writing if FIFO is full
always @(RFull or CharEn)
  NVWR = RFull | ~CharEn;

// Prevent reading if FIFO is empty
always @(ADD0 or REmpt or FIFOE)
  NVRD = ~(ADD0 & ~REmpt & FIFOE);

// Counter is held in reset when FIFOs are disabled
// Rx FIFO input counter
always @(posedge CLK or posedge MR)
begin
  if (MR)
    IP_A <= 0;
  else if (RRST) 	     
    IP_A <= OP_A;
  else if (~NVWR)
    IP_A <= IP_A + 1;
end


// Rx FIFO output counter
always @(posedge RD or posedge MR)
begin
  if (MR)
    OP_A <= 0;
  else if (~NVRD)
    OP_A <= OP_A + 1;
end	

// Works out difference between input and output pointers.
always @(IP_A or OP_A)
  ROffset = IP_A - OP_A;

// Detect when FIFO above the trigger level
always @(ROffset) 
begin
  RHold1  = (ROffset == 1);                 // Fifo holds 1 char of information
  RxTrig1 = (ROffset >= 1);    
  RxTrig2 = (ROffset >= 4);
  RxTrig3 = (ROffset >= 8);
  RxTrig4 = (ROffset >= 14);
end

always @(RTM or RTL or RxTrig1 or RxTrig2 or RxTrig3 or RxTrig4)
begin
  case ({RTM,RTL})
    2'b00   : RxAboveTrig = RxTrig1;
    2'b01   : RxAboveTrig = RxTrig2;
    2'b10   : RxAboveTrig = RxTrig3;
    default : RxAboveTrig = RxTrig4;
  endcase
end


// Decide if fifo is empty or full
always @(ROffset)
begin
  REmpt = (ROffset == 0);
  RFull = ROffset[4];
end

// Fifo mode OE indicator

always @(posedge CLK or posedge MR)
  if (MR)
    DOER <= 0;
  else if (RRST)      
    DOER <= DOE;
  else if (RFull & CharEn)
    DOER <= ~DOE;

always @(posedge NRD or posedge MR)
  if (MR)
    DOE <= 0;
  else if (ADD5 & FOE)
    DOE <= DOER;

always @(DOE or DOER)
  FOE = DOE ^ DOER;

// OP_A and IP_A reduced by 1 bit for exporting to upper level
always @(IP_A or OP_A)
begin
  RIP_A = IP_A[3:0];
  ROP_A = OP_A[3:0];
end

// Detect when FIFO is at trigger level
always @(RTM or RTL or ROffset)
  case ({RTM,RTL})
    2'b00 :
         if (ROffset == 1) Trigger = 1;
         else Trigger = 0;
    2'b01 :
         if (ROffset == 4) Trigger = 1;
         else Trigger = 0;
    2'b10 :
         if (ROffset == 8) Trigger = 1;
         else Trigger = 0;
    default :
         if (ROffset == 14) Trigger = 1;
         else Trigger = 0;
  endcase

endmodule