triginv.vhd

一个用FPGA实现的16FFT,仅供参考不作为工程文件

-- output of CoreGen module generator
-- $Header: romrVHT.vhd,v 1.3 1998/06/15 16:22:02 tonyw Exp $
-- *****************************************************************
--  Copyright 1997-1998 - Xilinx, Inc.
--  All rights reserved.
-- *****************************************************************
--
--  Description:
--    Behaviorial Model for 16 words by xx ROM LUT
--

library ieee;
use ieee.std_logic_1164.all;
--  
library xul;
use xul.ul_utils.all;
--
ENTITY triginv IS  
  PORT (a	: IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
        c	: IN STD_LOGIC;
        ce	: IN STD_LOGIC := default_fdce_ce;
        clr	: IN STD_LOGIC := default_fdce_clr;
        q	: OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0));
END triginv;
--
--  behavior describing a parameterized ROM
ARCHITECTURE behv OF triginv IS
--
CONSTANT width: INTEGER := 2;
CONSTANT depth: INTEGER := 16;
CONSTANT adrwid: INTEGER := 4;
CONSTANT usetbufrlocs: BOOLEAN := false;
CONSTANT rloc_x: rloctype := default_rloc;
CONSTANT rloc_y: rloctype := default_rloc;
CONSTANT userpm: rpmflagtype := yes_rpm;
CONSTANT huset : husettype := default_huset;
CONSTANT memdata: memdatatype(0 TO 255) := 
            (1,
            1,
            1,
            1,
            1,
            0,
            0,
            0,
            1,
            0,
            0,
            0,
            1,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
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            0,
            0,
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            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
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            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0);
--
BEGIN
-- 
 PROCESS (c, clr)
 BEGIN
   IF (rat(clr) = 'X') THEN
     q <= setallX(width);
   ELSIF (rat(clr) = '1') THEN
     q <= setall0(width);
   ELSIF (rat(c) = 'X' AND rat(c'LAST_VALUE) /= 'X' AND rat(ce) /= '0') THEN
     q <= setallX(width);
   ELSIF (c'EVENT and rat(c) = '1' AND rat(c'LAST_VALUE) = '0') THEN
     IF (rat(ce) = 'X') THEN
       q <= setallX(width);
     ELSIF (rat(ce) = '1') THEN
       IF (anyX(a)) THEN
         q <= setallX(width);
       ELSE
         q <= int_2_std_logic_vector(memdata(std_logic_vector_2_posint(a)), width);
       END IF;
     END IF;
   END IF;
 END PROCESS;
END behv;