__projnav.log

来自「一个简单的探测110三位的探测器」· LOG 代码 · 共 284 行

LOG
284 行
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Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".

Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".

Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".

Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Compiling vhdl file D:/Model/lab3/detector.vhf in Library work.Entity <detector> (Architecture <behavioral>) compiled.


Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.ERROR:DesignEntry:2 - Net "Y" needs to be connected to pins or IO Ports.WARNING:DesignEntry:11 - Net "XLXN_63" is connected to load pins and/or IO Port,   but there is no source pin or IO Port connected to itError: Process "View VHDL Functional Model" did not complete.
Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.ERROR:DesignEntry:2 - Net "Y" needs to be connected to pins or IO Ports.WARNING:DesignEntry:11 - Net "XLXN_63" is connected to load pins and/or IO Port,   but there is no source pin or IO Port connected to itError: Process "View VHDL Functional Model" did not complete.
Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".

Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.WARNING:DesignEntry:11 - Net "XLXN_100" is connected to load pins and/or IO   Port, but there is no source pin or IO Port connected to itDRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.WARNING:DesignEntry:11 - Net "XLXN_100" is connected to load pins and/or IO   Port, but there is no source pin or IO Port connected to itDRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Compiling vhdl file D:/Model/lab3/detector.vhf in Library work.Entity <detector> (Architecture <behavioral>) compiled.


Project Navigator Auto-Make Log File-------------------------------------



Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 6.1i - sch2vhdl G.23Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Compiling vhdl file D:/Model/lab3/detector.vhf in Library work.Entity <detector> (Architecture <behavioral>) compiled.

__projnav.log - 源码说明

本页面展示了「一个简单的探测110三位的探测器」中的 __projnav.log 源码文件，采用 LOG 编程语言编写，共 284 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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