transcript

来自「一个简单的探测110三位的探测器」· 代码 · 共 57 行

# Reading D:/Modeltech_6.0d/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0d Apr 25 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do testwave.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package vcomponents
# -- Compiling entity detector
# -- Compiling architecture behavioral of detector
# Model Technology ModelSim SE vcom 6.0d Compiler 2005.04 Apr 25 2005
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity testwave
# -- Compiling architecture testbench_arch of testwave
# -- Compiling configuration detector_cfg
# -- Loading entity testwave
# -- Loading architecture testbench_arch of testwave
# -- Loading package vcomponents
# -- Loading entity detector
# vsim -lib work -t 1ps testwave 
# Loading d:\Modeltech_6.0d\win32/../std.standard
# Loading d:\Modeltech_6.0d\win32/../ieee.std_logic_1164(body)
# Loading d:\Modeltech_6.0d\win32/../ieee.numeric_std(body)
# Loading d:\Modeltech_6.0d\win32/../std.textio(body)
# Loading d:\Modeltech_6.0d\win32/../ieee.std_logic_textio(body)
# Loading work.testwave(testbench_arch)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.vcomponents
# Loading work.detector(behavioral)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.fd(fd_v)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.and2(and2_v)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.or2(or2_v)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.inv(inv_v)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.or3(or3_v)
# Loading d:\Modeltech_6.0d\win32/../xilinx/vhdl/unisim.and3(and3_v)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected. 
#    Time: 305 ns  Iteration: 0  Process: /testwave/line__61 File: testwave.vhw
# Break at testwave.vhw line 166
# Simulation Breakpoint: Break at testwave.vhw line 166
# MACRO ./testwave.fdo PAUSED at line 13