detector.vhd

一个简单的探测110三位的探测器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity detector3 is
 Port (   A: in std_logic;      --input signal 
          clk:  in std_logic;    --clock signal 
		rst:  in std_logic;    -- reset signal 
       	Y:  out std_logic);   -- out signal 
end detector3;

architecture Behavioral of detector3 is
  type STATE_TYPE is (S1, S2, S3, S4);
 
--Remove these two lines to allow Express to determine the encoding
--attribute ENUM_ENCODING: STRING;
--attribute ENUM_ENCODING of STATE_TYPE: type is "00 01 10 11";
 
signal CS, NS: STATE_TYPE;
begin


 
--**Insert the following after the 'begin' keyword**
    SYNC_PROC: process (clk, rst)
    begin
       if (rst='1') then
              CS <= S1;
       elsif (clk'event and clk = '1') then
	  	  IF ( CS = S4 AND A = '1') THEN CS <= S2;
            ELSIF ( CS = S1 AND A = '1') THEN CS <= S2;
		  ELSIF ( CS = S2 AND A = '1') THEN CS <= S3;
		  ELSIF ( CS = S3 AND A = '0' ) THEN CS <=S4;
		  ELSIF ( CS =S3 AND A = '1') THEN NULL;
		  ELSE CS <= S1;
		  END IF;
       end if;
    end process;
 
    COMB_PROC: process (CS)
    begin
       IF CS = S4 THEN Y <= '1';
	  ELSE Y <= '0';
	  END IF;
    end process; 

end Behavioral;