testwave4.vhw

一个简单的探测110三位的探测器

-- D:\MODEL\LAB4
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Jun 16 20:56:10 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testwave4 IS
END testwave4;

ARCHITECTURE testbench_arch OF testwave4 IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT detector3
		PORT (
			A : in  std_logic;
			clk : in  std_logic;
			rst : in  std_logic;
			Y : out  std_logic
		);
	END COMPONENT;

	SIGNAL A : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL rst : std_logic;
	SIGNAL Y : std_logic;

BEGIN
	UUT : detector3
	PORT MAP (
		A => A,
		clk => clk,
		rst => rst,
		Y => Y
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 5 ns;
		clk <= transport '1';
		WAIT FOR 5 ns;
		WAIT FOR 5 ns;
		clk <= transport '0';
		WAIT FOR 5 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Y(
			next_Y : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Y /= next_Y) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Y="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Y);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Y);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		A <= transport '0';
		rst <= transport '1';
		-- --------------------
		WAIT FOR 10 ns; -- Time=10 ns
		CHECK_Y('0',10);
		-- --------------------
		WAIT FOR 10 ns; -- Time=20 ns
		A <= transport '1';
		rst <= transport '0';
		-- --------------------
		WAIT FOR 10 ns; -- Time=30 ns
		CHECK_Y('0',30);
		-- --------------------
		WAIT FOR 20 ns; -- Time=50 ns
		CHECK_Y('0',50);
		-- --------------------
		WAIT FOR 10 ns; -- Time=60 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 10 ns; -- Time=70 ns
		CHECK_Y('1',70);
		-- --------------------
		WAIT FOR 10 ns; -- Time=80 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 10 ns; -- Time=90 ns
		CHECK_Y('0',90);
		-- --------------------
		WAIT FOR 10 ns; -- Time=100 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 10 ns; -- Time=110 ns
		CHECK_Y('0',110);
		-- --------------------
		WAIT FOR 10 ns; -- Time=120 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 10 ns; -- Time=130 ns
		CHECK_Y('0',130);
		-- --------------------
		WAIT FOR 20 ns; -- Time=150 ns
		CHECK_Y('0',150);
		-- --------------------
		WAIT FOR 20 ns; -- Time=170 ns
		CHECK_Y('0',170);
		-- --------------------
		WAIT FOR 10 ns; -- Time=180 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 10 ns; -- Time=190 ns
		CHECK_Y('1',190);
		-- --------------------
		WAIT FOR 10 ns; -- Time=200 ns
		A <= transport '1';
		-- --------------------
		WAIT FOR 10 ns; -- Time=210 ns
		CHECK_Y('0',210);
		-- --------------------
		WAIT FOR 20 ns; -- Time=230 ns
		CHECK_Y('0',230);
		-- --------------------
		WAIT FOR 10 ns; -- Time=240 ns
		A <= transport '0';
		-- --------------------
		WAIT FOR 10 ns; -- Time=250 ns
		CHECK_Y('1',250);
		-- --------------------
		WAIT FOR 20 ns; -- Time=270 ns
		CHECK_Y('0',270);
		-- --------------------
		WAIT FOR 35 ns; -- Time=305 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION detector3_cfg OF testwave4 IS
	FOR testbench_arch
	END FOR;
END detector3_cfg;