lru_new.v

采用LRU替换算法。这种算法选择最久没有被访问的块作为被替换的块。 为了实现LRU算法

`timescale 1ns/1ns
module lru_ram (gp_addr,MCLK,nRESET,miss,hit0,hit1,hit2,hit3,miss_cache_ram_addr, miss_clr,hit0_clr,hit1_clr,hit2_clr,hit3_clr,lru_addr,substitute);
input [5:0] gp_addr;
input MCLK;
input nRESET;
input miss;
input hit0;
input hit1;
input hit2;
input hit3;
output [7:0] miss_cache_ram_addr;
output miss_clr;
output hit0_clr;
output hit1_clr;
output hit2_clr;
output hit3_clr;
output [5:0] lru_addr;
output [1:0] substitute;
reg    [1:0] substitute;

wire    [7:0] lru_do;
wire    [7:0] lru_di;

wire   [5:0] lru_addr;
reg    [7:0] lru_ram [63:0];
reg    [1:0] cnt0;
reg    [1:0] cnt1;
reg    [1:0] cnt2;
reg    [1:0] cnt3;
wire [7:0] miss_cache_ram_addr;

assign lru_addr = gp_addr;
assign lru_di ={cnt0,cnt1,cnt2,cnt3};
assign miss_cache_ram_addr = {gp_addr,substitute[1:0]};

integer i;

initial begin
  for (i=0; i<64; i=i+1)
    lru_ram[i] <= 8'h0;
  end


 wire lru_wr0 = hit0 | hit1 | hit2 | hit3 | miss;
 reg lru_wr_r1, lru_wr_r2;
 
 always @ (negedge MCLK or negedge nRESET)
   begin
   if (nRESET == 1'd0)
     begin
     lru_wr_r1 <= 1'd0;
     lru_wr_r2 <= 1'd0;
     end
   else
     begin
     lru_wr_r1 <= lru_wr0;
     lru_wr_r2 <= lru_wr_r1;
     end
   end
wire lru_rd = ! ( !lru_wr_r1 & lru_wr0);     //read first
wire lru_wr = ! ( !lru_wr_r2 & lru_wr_r1);   //write second
wire lru_en = (!lru_wr_r1 & lru_wr0);

reg miss_clr_r1, miss_clr_r2;
always @ (negedge MCLK or negedge nRESET)
  begin
  if (nRESET == 1'd0)
    begin
    miss_clr_r1 <= 1'd0;
    miss_clr_r2 <= 1'd0;
    end
  else 
    begin
    miss_clr_r1 <= miss;
    miss_clr_r2 <= miss_clr_r1;
    end
  end
  
wire miss_clr = miss_clr_r1 & !miss_clr_r2; 

reg hit0_clr_r1, hit0_clr_r2;
always @ (negedge MCLK or negedge nRESET) 
  begin                                  
  if (nRESET == 1'd0)                    
    begin                                
    hit0_clr_r1 <= 1'd0;                 
    hit0_clr_r2 <= 1'd0;                 
    end                                  
  else                                   
    begin                                
    hit0_clr_r1 <= hit0;                 
    hit0_clr_r2 <= hit0_clr_r1;          
    end                                  
  end                                    
wire hit0_clr = hit0_clr_r1 & !hit0_clr_r2;

reg hit1_clr_r1, hit1_clr_r2;
always @ (negedge MCLK or negedge nRESET) 
  begin                                  
  if (nRESET == 1'd0)                    
    begin                                
    hit1_clr_r1 <= 1'd0;                 
    hit1_clr_r2 <= 1'd0;                 
    end                                  
  else                                   
    begin                                
    hit1_clr_r1 <= hit1;                 
    hit1_clr_r2 <= hit1_clr_r1;          
    end                                  
  end                                    
wire hit1_clr = hit1_clr_r1 & !hit1_clr_r2;

reg hit2_clr_r1, hit2_clr_r2;
always @ (negedge MCLK or negedge nRESET) 
  begin                                  
  if (nRESET == 1'd0)                    
    begin                                
    hit2_clr_r1 <= 1'd0;                 
    hit2_clr_r2 <= 1'd0;                 
    end                                  
  else                                   
    begin                                
    hit2_clr_r1 <= hit2;                 
    hit2_clr_r2 <= hit2_clr_r1;          
    end                                  
  end                                    
wire hit2_clr = hit2_clr_r1 & !hit2_clr_r2;

reg hit3_clr_r1, hit3_clr_r2;
always @ (negedge MCLK or negedge nRESET) 
  begin                                  
  if (nRESET == 1'd0)                    
    begin                                
    hit3_clr_r1 <= 1'd0;                 
    hit3_clr_r2 <= 1'd0;                 
    end                                  
  else                                   
    begin                                
    hit3_clr_r1 <= hit3;                 
    hit3_clr_r2 <= hit3_clr_r1;          
    end                                  
  end                                    
wire hit3_clr = hit3_clr_r1 & !hit3_clr_r2;


always @ (negedge lru_wr)
 begin
  if(!lru_wr)
     lru_ram[lru_addr] <= lru_di;  
 end

wire [1:0]   cntr0 = lru_do[7:6];
wire [1:0]   cntr1 = lru_do[5:4];
wire [1:0]   cntr2 = lru_do[3:2];
wire [1:0]   cntr3 = lru_do[1:0]; 

 
assign lru_do = (lru_rd == 1'd0) ? lru_ram[lru_addr] : 8'bz;
always @(negedge MCLK or negedge nRESET or gp_addr)
begin
  if(!nRESET)
   begin
   cnt0 <= 2'b00;
   cnt1 <= 2'b00;
   cnt2 <= 2'b00;
   cnt3 <= 2'b00;
   substitute <= 2'b00;
   end
  else if (lru_en)
    begin
 
     if (hit0|hit1|hit2|hit3)
      begin 
      case({hit0,hit1,hit2,hit3})
      4'b1000: begin
                 cnt0 <= 2'b00;
                 cnt1 <= (cntr1 < cntr0) ? cntr1+1:cntr1; 
                 cnt2 <= (cntr2 < cntr0) ? cntr2+1:cntr2;
                 cnt3 <= (cntr3 < cntr0) ? cntr3+1:cntr3;  
                 //lru_wr <= 1;
               end   
      4'b0100: begin
                 cnt0 <= (cntr0 < cntr1) ? cntr0+1:cntr0;
                 cnt1 <= 2'b00; 
                 cnt2 <= (cntr2 < cntr1) ? cntr2+1:cntr2;
                 cnt3 <= (cntr3 < cntr1) ? cntr3+1:cntr3; 
                 //lru_wr <= 1;
               end
      4'b0010: begin
                 cnt0 <= (cntr0 < cntr2) ? cntr0+1:cntr0;
                 cnt1 <= (cntr1 < cntr2) ? cntr1+1:cntr1; 
                 cnt2 <= 2'b00;
                 cnt3 <= (cntr3 < cntr2) ? cntr3+1:cntr3;
                 //lru_wr <= 1;
               end   
      4'b0001: begin
                 cnt0 <= (cntr0 < cntr3) ? cntr0+1:cntr0;
                 cnt1 <= (cntr1 < cntr3) ? cntr1+1:cntr1; 
                 cnt2 <= (cntr2 < cntr3) ? cntr2+1:cntr2;
                 cnt3 <= 2'b00;
                 //lru_wr <= 1;
               end
       endcase
       end  
     else if (miss)
       begin
          if (cntr0 == 2'b11)
             begin
               substitute <= 2'b00;
               cnt0 <= 2'b00;
               cnt1 <=  cntr1+1; 
               cnt2 <=  cntr2+1;
               cnt3 <=  cntr3+1;  
               //lru_wr <= 1;
             end
          else if (cntr1 == 2'b11)
             begin
               substitute <= 2'b01;
               cnt0 <=  cntr0+1;
               cnt1 <=  2'b00; 
               cnt2 <=  cntr2+1;
               cnt3 <=  cntr3+1; 
               //lru_wr <= 1; 
             end     
          else if (cntr2 == 2'b11)
             begin
               substitute <= 2'b10;
               cnt0 <=  cntr0+1;
               cnt1 <=  cntr1+1; 
               cnt2 <=  2'b00;
               cnt3 <=  cntr3+1;  
               //lru_wr <= 1;
             end     
          else if (cntr3 == 2'b11)
             begin
               substitute <= 2'b11;
               cnt0 <=  cntr0+1;
               cnt1 <=  cntr1+1; 
               cnt2 <=  cntr2+1;
               cnt3 <=  2'b00;  
               //lru_wr <= 1;
             end
          else if (cntr0 == 2'b00 & cntr1 == 2'b00& cntr2 == 2'b00& cntr3 == 2'b00)
             begin
               substitute <= 2'b00;
               cnt0 <=  2'b00;
               cnt1 <=  cntr1+1; 
               cnt2 <=  cntr2+1;
               cnt3 <=  cntr3+1;  
               //lru_wr <= 1;
             end    
          else if (cntr0 == 2'b00)
             begin
               substitute <= 2'b01;
               cnt0 <=  cntr0+1;
               cnt1 <=  2'b00; 
               cnt2 <=  cntr2+1;
               cnt3 <=  cntr3+1;  
               //lru_wr <= 1;
             end              
          else if (cntr1 == 2'b00)
             begin
               substitute <= 2'b10;
               cnt0 <=  cntr0+1;
               cnt1 <=  cntr1+1; 
               cnt2 <=  2'b00;
               cnt3 <=  cntr3+1;  
               //lru_wr <= 1;
             end   
          else if (cntr2 == 2'b00)
             begin
               substitute <= 2'b11;
               cnt0 <=  cntr0+1;
               cnt1 <=  cntr1+1; 
               cnt2 <=  cntr2+1;
               cnt3 <=  2'b00;  
               //lru_wr <= 1;
             end                              

                        
          
  
                   
        end            //miss
       end
     end
 
   endmodule