adsu1.vhd

来自「xilinx xc9572 cpld 实现的伺服电机控制器」· VHDL 代码 · 共 47 行

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_1660_5
-- /___/   /\     Timestamp : 04/05/2006 13:21:06
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: copy_of_adsu1
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity copy_of_adsu1 is
   port ( ADD : in    std_logic; 
          A0  : in    std_logic; 
          B0  : in    std_logic; 
          CI  : in    std_logic; 
          CO  : out   std_logic; 
          S0  : out   std_logic);
end copy_of_adsu1;

architecture BEHAVIORAL of copy_of_adsu1 is
begin
end BEHAVIORAL;

-- synopsys translate_off
configuration CFG_copy_of_adsu1 of  copy_of_adsu1 is
   for BEHAVIORAL
   end for;
end CFG_copy_of_adsu1;
-- synopsys translate_on