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来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 934 行 · 第 1/4 页
RPT
934 行
FTCPE_XLXI_57/Q410: FTCPE port map (XLXI_57/Q41(0),XLXI_57/Q41_T(0),NOT XLXI_57/Q41(2)/XLXI_57/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
XLXI_57/Q41_T(0) <= ((MA1 AND NOT MB1)
OR (NOT MA1 AND MB1));
FTCPE_XLXI_57/Q411: FTCPE port map (XLXI_57/Q41(1),XLXI_57/Q41_T(1),NOT XLXI_57/Q41(2)/XLXI_57/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
XLXI_57/Q41_T(1) <= ((MA1 AND NOT MB1 AND XLXI_57/Q41(0).FBK.LFBK)
OR (NOT MA1 AND MB1 AND NOT XLXI_57/Q41(0).FBK.LFBK));
FTCPE_XLXI_57/Q412: FTCPE port map (XLXI_57/Q41(2),XLXI_57/Q41_T(2),NOT XLXI_57/Q41(2)/XLXI_57/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
XLXI_57/Q41_T(2) <= ((MA1 AND NOT MB1 AND XLXI_57/Q41(0).FBK.LFBK AND
XLXI_57/Q41(1).FBK.LFBK)
OR (NOT MA1 AND MB1 AND NOT XLXI_57/Q41(0).FBK.LFBK AND
NOT XLXI_57/Q41(1).FBK.LFBK));
XLXI_57/Q41(2)/XLXI_57/Q41(2)_CLKF__$INT <= (MA1 AND MB1 AND NOT MC1);
FTCPE_XLXI_57/Q413: FTCPE port map (XLXI_57/Q41(3),XLXI_57/Q41_T(3),NOT XLXI_57/Q41(2)/XLXI_57/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
XLXI_57/Q41_T(3) <= ((MA1 AND NOT MB1 AND XLXI_57/Q41(3).FBK.LFBK)
OR (NOT MA1 AND MB1 AND NOT XLXI_57/Q41(3).FBK.LFBK));
FTCPE_XLXI_57/Q40: FTCPE port map (XLXI_57/Q4(0),XLXI_57/Q4_T(0),NOT XLXI_57/Q4(2)/XLXI_57/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
XLXI_57/Q4_T(0) <= ((MA0 AND NOT MB0)
OR (NOT MA0 AND MB0));
FTCPE_XLXI_57/Q41: FTCPE port map (XLXI_57/Q4(1),XLXI_57/Q4_T(1),NOT XLXI_57/Q4(2)/XLXI_57/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
XLXI_57/Q4_T(1) <= ((MA0 AND NOT MB0 AND XLXI_57/Q4(0).FBK.LFBK)
OR (NOT MA0 AND MB0 AND NOT XLXI_57/Q4(0).FBK.LFBK));
FTCPE_XLXI_57/Q42: FTCPE port map (XLXI_57/Q4(2),XLXI_57/Q4_T(2),NOT XLXI_57/Q4(2)/XLXI_57/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
XLXI_57/Q4_T(2) <= ((MA0 AND NOT MB0 AND XLXI_57/Q4(0).FBK.LFBK AND
XLXI_57/Q4(1).FBK.LFBK)
OR (NOT MA0 AND MB0 AND NOT XLXI_57/Q4(0).FBK.LFBK AND
NOT XLXI_57/Q4(1).FBK.LFBK));
XLXI_57/Q4(2)/XLXI_57/Q4(2)_CLKF__$INT <= (MA0 AND MB0 AND NOT MC0);
FTCPE_XLXI_57/Q43: FTCPE port map (XLXI_57/Q4(3),XLXI_57/Q4_T(3),NOT XLXI_57/Q4(2)/XLXI_57/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
XLXI_57/Q4_T(3) <= ((MA0 AND NOT MB0 AND XLXI_57/Q4(3).FBK.LFBK)
OR (NOT MA0 AND MB0 AND NOT XLXI_57/Q4(3).FBK.LFBK));
FDCPE_XLXN_80: FDCPE port map (XLXN_8(0),'0','0',XLXN_8_CLR(0),XLXN_8_PRE(0));
XLXN_8_CLR(0) <= (NOT XLXI_57/Q4(0) AND NOT RD);
XLXN_8_PRE(0) <= (XLXI_57/Q4(0) AND NOT RD);
FDCPE_XLXN_81: FDCPE port map (XLXN_8(1),'0','0',XLXN_8_CLR(1),XLXN_8_PRE(1));
XLXN_8_CLR(1) <= (NOT XLXI_57/Q4(1) AND NOT RD);
XLXN_8_PRE(1) <= (XLXI_57/Q4(1) AND NOT RD);
FDCPE_XLXN_82: FDCPE port map (XLXN_8(2),'0','0',XLXN_8_CLR(2),XLXN_8_PRE(2));
XLXN_8_CLR(2) <= (NOT RD AND NOT XLXI_57/Q4(2).FBK.LFBK);
XLXN_8_PRE(2) <= (NOT RD AND XLXI_57/Q4(2).FBK.LFBK);
FDCPE_XLXN_83: FDCPE port map (XLXN_8(3),'0','0',XLXN_8_CLR(3),XLXN_8_PRE(3));
XLXN_8_CLR(3) <= (NOT RD AND NOT XLXI_57/Q4(3).FBK.LFBK);
XLXN_8_PRE(3) <= (NOT RD AND XLXI_57/Q4(3).FBK.LFBK);
FDCPE_XLXN_84: FDCPE port map (XLXN_8(4),'0','0',XLXN_8_CLR(4),XLXN_8_PRE(4));
XLXN_8_CLR(4) <= (NOT RD AND NOT XLXI_57/Q41(0).FBK.LFBK);
XLXN_8_PRE(4) <= (NOT RD AND XLXI_57/Q41(0).FBK.LFBK);
FDCPE_XLXN_85: FDCPE port map (XLXN_8(5),'0','0',XLXN_8_CLR(5),XLXN_8_PRE(5));
XLXN_8_CLR(5) <= (NOT RD AND NOT XLXI_57/Q41(1).FBK.LFBK);
XLXN_8_PRE(5) <= (NOT RD AND XLXI_57/Q41(1).FBK.LFBK);
FDCPE_XLXN_86: FDCPE port map (XLXN_8(6),'0','0',XLXN_8_CLR(6),XLXN_8_PRE(6));
XLXN_8_CLR(6) <= (NOT RD AND NOT XLXI_57/Q41(2).FBK.LFBK);
XLXN_8_PRE(6) <= (NOT RD AND XLXI_57/Q41(2).FBK.LFBK);
FDCPE_XLXN_87: FDCPE port map (XLXN_8(7),'0','0',XLXN_8_CLR(7),XLXN_8_PRE(7));
XLXN_8_CLR(7) <= (NOT RD AND NOT XLXI_57/Q41(3).FBK.LFBK);
XLXN_8_PRE(7) <= (NOT RD AND XLXI_57/Q41(3).FBK.LFBK);
D_I(3) <= D(3)_BUFR;
D(3) <= D_I(3) when D_OE(3) = '1' else 'Z';
D_OE(3) <= (NOT CS AND A2);
D_I(7) <= D(7)_BUFR;
D(7) <= D_I(7) when D_OE(7) = '1' else 'Z';
D_OE(7) <= (NOT CS AND A2);
D_I(6) <= D(6)_BUFR;
D(6) <= D_I(6) when D_OE(6) = '1' else 'Z';
D_OE(6) <= (NOT CS AND A2);
D_I(5) <= D(5)_BUFR;
D(5) <= D_I(5) when D_OE(5) = '1' else 'Z';
D_OE(5) <= (NOT CS AND A2);
D_I(4) <= D(4)_BUFR;
D(4) <= D_I(4) when D_OE(4) = '1' else 'Z';
D_OE(4) <= (NOT CS AND A2);
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC9572-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TIE 51 VCC
2 NC 52 MC1
3 TIE 53 MR_2<2>
4 TIE 54 MR_2<1>
5 VCC 55 MC0
6 ALMR 56 MB0
7 NC 57 VCC
8 CLK 58 M2PS
9 WR 59 SPDB1
10 INT_L0 60 SPD2A
11 INT0 61 MB1
12 A0 62 GND
13 D<1> 63 MA1
14 D<4> 64 MR_1<1>
15 D<5> 65 MA0
16 D<0> 66 MR_1<0>
17 D<7> 67 MR_1<4>
18 D<2> 68 MR_1<7>
19 NC 69 GND
20 D<3> 70 MR_0<0>
21 GND 71 MR_1<2>
22 CLK8 72 MR_1<3>
23 RD 73 NC
24 NC 74 MR_0<2>
25 D<6> 75 GND
26 VCC 76 MR_1<5>
27 A1 77 MR_1<6>
28 CS 78 MR_0<5>
29 A2 79 PC2ON
30 UART0 80 NC
31 GND 81 MR_0<1>
32 MR_2<6> 82 MR_0<3>
33 TIE 83 TDO
34 NC 84 GND
35 MR_2<3> 85 MR_0<4>
36 SEN2 86 MR_0<7>
37 MR_2<0> 87 M1PS
38 VCC 88 VCC
39 M2CLR 89 MR_0<6>
40 M2SG 90 SEN0
41 MR_2<7> 91 M1SG
42 SPDB2 92 REL0
43 NC 93 M1CLR
44 GND 94 SPDA1
45 TDI 95 SEN1
46 NC 96 PC1ON
47 TMS 97 CS1
48 TCK 98 VCC
49 MR_2<5> 99 RESET
50 MR_2<4> 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : AUTO
Ground on Unused IOs : OFF
Global Clock Optimization : OFF
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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