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来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 934 行 · 第 1/4 页

    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.


ALMR <= NOT ((NOT MR_1(2) AND NOT MR_1(1) AND NOT MR_1(0)));


CLK <= CLK8;

FTCPE_CLR0: FTCPE port map (CLR0,CLR0_T,WR,NOT RESET,'0');
CLR0_T <= ((NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND D(7).PIN AND NOT CLR0.FBK.LFBK)
	OR (NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND CLR0.FBK.LFBK));

FTCPE_CLR1: FTCPE port map (CLR1,CLR1_T,WR,NOT RESET,'0');
CLR1_T <= ((D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND D(7).PIN AND NOT CLR1.FBK.LFBK)
	OR (D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND CLR1.FBK.LFBK));


CS1 <= NOT ((NOT CS AND NOT A2 AND NOT A1 AND NOT A0));

FTCPE_CSA1: FTCPE port map (CSA1,CSA1_T,WR,NOT RESET,'0');
CSA1_T <= ((NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND NOT CSA1.FBK.LFBK)
	OR (NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND CSA1.FBK.LFBK));

FTCPE_CSA2: FTCPE port map (CSA2,CSA2_T,WR,NOT RESET,'0');
CSA2_T <= ((D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND NOT CSA2.FBK.LFBK)
	OR (D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND CSA2.FBK.LFBK));

FTCPE_CS_U: FTCPE port map (CS_U,CS_U_T,WR,NOT RESET,'0');
CS_U_T <= ((NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND D(7).PIN AND NOT CS_U.FBK.LFBK)
	OR (NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND CS_U.FBK.LFBK));


D(3)_BUFR <= ((A1 AND A0 AND XLXN_8(3).FBK.LFBK)
	OR (A1 AND NOT A0 AND MR_2(3))
	OR (NOT A1 AND A0 AND MR_1(3))
	OR (NOT A1 AND NOT A0 AND MR_0(3)));


D(4)_BUFR <= ((A1 AND A0 AND XLXN_8(4))
	OR (A1 AND NOT A0 AND MR_2(4))
	OR (NOT A1 AND A0 AND MR_1(4))
	OR (NOT A1 AND NOT A0 AND MR_0(4)));


D(5)_BUFR <= ((A1 AND A0 AND XLXN_8(5).FBK.LFBK)
	OR (A1 AND NOT A0 AND MR_2(5))
	OR (NOT A1 AND A0 AND MR_1(5))
	OR (NOT A1 AND NOT A0 AND MR_0(5)));


D(6)_BUFR <= ((A1 AND A0 AND XLXN_8(6))
	OR (A1 AND NOT A0 AND MR_2(6))
	OR (NOT A1 AND A0 AND MR_1(6))
	OR (NOT A1 AND NOT A0 AND MR_0(6)));


D(7)_BUFR <= ((A1 AND A0 AND XLXN_8(7).FBK.LFBK)
	OR (A1 AND NOT A0 AND MR_2(7))
	OR (NOT A1 AND A0 AND MR_1(7))
	OR (NOT A1 AND NOT A0 AND MR_0(7)));


D_I(0) <= ((A1 AND A0 AND XLXN_8(0))
	OR (A1 AND NOT A0 AND MR_2(0))
	OR (NOT A1 AND A0 AND MR_1(0))
	OR (NOT A1 AND NOT A0 AND MR_0(0)));
D(0) <= D_I(0) when D_OE(0) = '1' else 'Z';
D_OE(0) <= (NOT CS AND A2);


D_I(1) <= ((A1 AND A0 AND XLXN_8(1))
	OR (A1 AND NOT A0 AND MR_2(1))
	OR (NOT A1 AND A0 AND MR_1(1))
	OR (NOT A1 AND NOT A0 AND MR_0(1)));
D(1) <= D_I(1) when D_OE(1) = '1' else 'Z';
D_OE(1) <= (NOT CS AND A2);


D_I(2) <= ((A1 AND A0 AND XLXN_8(2))
	OR (A1 AND NOT A0 AND MR_2(2))
	OR (NOT A1 AND A0 AND MR_1(2))
	OR (NOT A1 AND NOT A0 AND MR_0(2)));
D(2) <= D_I(2) when D_OE(2) = '1' else 'Z';
D_OE(2) <= (NOT CS AND A2);


INT0 <= INT_L0;

FTCPE_M1CLR: FTCPE port map (M1CLR,M1CLR_T,WR,NOT RESET,'0');
M1CLR_T <= ((D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT M1CLR_OBUF.FBK.LFBK)
	OR (D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	M1CLR_OBUF.FBK.LFBK));

FTCPE_M1PS: FTCPE port map (M1PS,M1PS_T,WR,NOT RESET,'0');
M1PS_T <= ((NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT M1PS_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	M1PS_OBUF.FBK.LFBK));

FTCPE_M1SG: FTCPE port map (M1SG,M1SG_T,WR,NOT RESET,'0');
M1SG_T <= ((NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT M1SG_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	M1SG_OBUF.FBK.LFBK));

FTCPE_M2CLR: FTCPE port map (M2CLR,M2CLR_T,WR,NOT RESET,'0');
M2CLR_T <= ((D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT M2CLR_OBUF.FBK.LFBK)
	OR (D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	M2CLR_OBUF.FBK.LFBK));

FTCPE_M2PS: FTCPE port map (M2PS,M2PS_T,WR,NOT RESET,'0');
M2PS_T <= ((NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT M2PS_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	M2PS_OBUF.FBK.LFBK));

FTCPE_M2SG: FTCPE port map (M2SG,M2SG_T,WR,NOT RESET,'0');
M2SG_T <= ((NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT M2SG_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	M2SG_OBUF.FBK.LFBK));

FTCPE_PC1ON: FTCPE port map (PC1ON,PC1ON_T,WR,NOT RESET,'0');
PC1ON_T <= ((NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND D(2).PIN AND D(7).PIN AND 
	NOT PC1ON_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND 
	PC1ON_OBUF.FBK.LFBK));

FTCPE_PC2ON: FTCPE port map (PC2ON,PC2ON_T,WR,NOT RESET,'0');
PC2ON_T <= ((NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND D(7).PIN AND 
	NOT PC2ON_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND 
	PC2ON_OBUF.FBK.LFBK));

FTCPE_REL0: FTCPE port map (REL0,REL0_T,WR,NOT RESET,'0');
REL0_T <= ((D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT REL0_OBUF.FBK.LFBK)
	OR (D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	REL0_OBUF.FBK.LFBK));

FTCPE_SEN0: FTCPE port map (SEN0,SEN0_T,WR,NOT RESET,'0');
SEN0_T <= ((NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT SEN0_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	SEN0_OBUF.FBK.LFBK));

FTCPE_SEN1: FTCPE port map (SEN1,SEN1_T,WR,NOT RESET,'0');
SEN1_T <= ((D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT SEN1_OBUF.FBK.LFBK)
	OR (D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	SEN1_OBUF.FBK.LFBK));

FTCPE_SEN2: FTCPE port map (SEN2,SEN2_T,WR,NOT RESET,'0');
SEN2_T <= ((D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND D(7).PIN AND 
	NOT SEN2_OBUF.FBK.LFBK)
	OR (D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND NOT D(2).PIN AND NOT D(7).PIN AND 
	SEN2_OBUF.FBK.LFBK));

FTCPE_SPD2A: FTCPE port map (SPD2A,SPD2A_T,WR,NOT RESET,'0');
SPD2A_T <= ((NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND D(7).PIN AND 
	NOT SPD2A_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND 
	SPD2A_OBUF.FBK.LFBK));

FTCPE_SPDA1: FTCPE port map (SPDA1,SPDA1_T,WR,NOT RESET,'0');
SPDA1_T <= ((NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND D(2).PIN AND D(7).PIN AND 
	NOT SPDA1_OBUF.FBK.LFBK)
	OR (NOT D(1).PIN AND D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND 
	SPDA1_OBUF.FBK.LFBK));

FTCPE_SPDB1: FTCPE port map (SPDB1,SPDB1_T,WR,NOT RESET,'0');
SPDB1_T <= ((D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND D(2).PIN AND D(7).PIN AND 
	NOT SPDB1_OBUF.FBK.LFBK)
	OR (D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	NOT D(4).PIN AND D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND 
	SPDB1_OBUF.FBK.LFBK));

FTCPE_SPDB2: FTCPE port map (SPDB2,SPDB2_T,WR,NOT RESET,'0');
SPDB2_T <= ((D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND D(7).PIN AND 
	NOT SPDB2_OBUF.FBK.LFBK)
	OR (D(1).PIN AND NOT D(0).PIN AND NOT CS AND NOT A2 AND A1 AND NOT A0 AND 
	D(4).PIN AND NOT D(3).PIN AND D(2).PIN AND NOT D(7).PIN AND 
	SPDB2_OBUF.FBK.LFBK));


UART0 <= NOT (((CSA2 AND NOT CSA1 AND CS_U AND NOT MR_2(2))
	OR (NOT CSA2 AND CSA1 AND CS_U AND NOT MR_2(1))
	OR (NOT CSA2 AND NOT CSA1 AND CS_U AND NOT MR_2(0))));