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来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 934 行 · 第 1/4 页
RPT
934 行
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 29/7
Number of signals used by logic mapping into function block: 29
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
M1PS 4 0 0 1 FB2_1 STD 87 I/O O
SPDA1 4 0 0 1 FB2_2 STD 94 I/O O
M1SG 4 0 0 1 FB2_3 STD 91 I/O O
M1CLR 4 0 0 1 FB2_4 STD 93 I/O O
SEN1 4 0 0 1 FB2_5 STD 95 I/O O
PC1ON 4 0 0 1 FB2_6 STD 96 I/O O
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
CS1 1 0 0 4 FB2_8 STD 97 I/O O
(unused) 0 0 0 5 FB2_9 99 GSR/I/O I
CS_U 4 0 0 1 FB2_10 STD 1 I/O (b)
CSA2 4 0 0 1 FB2_11 STD 4 GTS/I/O (b)
ALMR 1 0 0 4 FB2_12 STD 6 I/O O
CLK 1 0 0 4 FB2_13 STD 8 I/O O
CSA1 4 0 0 1 FB2_14 STD 9 I/O I
INT0 1 0 0 4 FB2_15 STD 11 I/O O
CLR1 4 0 0 1 FB2_16 STD 10 I/O I
CLR0 4 0 0 1 FB2_17 STD 12 I/O I
REL0 4 0 0 1 FB2_18 STD 92 I/O O
Signals Used by Logic in Function Block
1: A0 11: INT_L0 21: D<3>.PIN
2: A1 12: M1CLR_OBUF.FBK.LFBK
22: D<4>.PIN
3: A2 13: M1PS_OBUF.FBK.LFBK
23: D<7>.PIN
4: CLK8 14: M1SG_OBUF.FBK.LFBK
24: PC1ON_OBUF.FBK.LFBK
5: CLR0.FBK.LFBK 15: MR_1<0> 25: REL0_OBUF.FBK.LFBK
6: CLR1.FBK.LFBK 16: MR_1<1> 26: RESET
7: CSA1.FBK.LFBK 17: MR_1<2> 27: SEN1_OBUF.FBK.LFBK
8: CSA2.FBK.LFBK 18: D<0>.PIN 28: SPDA1_OBUF.FBK.LFBK
9: CS 19: D<1>.PIN 29: WR
10: CS_U.FBK.LFBK 20: D<2>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
M1PS XXX.....X...X....XXXXXX..X..X........... 13 13
SPDA1 XXX.....X........XXXXXX..X.XX........... 13 13
M1SG XXX.....X....X...XXXXXX..X..X........... 13 13
M1CLR XXX.....X..X.....XXXXXX..X..X........... 13 13
SEN1 XXX.....X........XXXXXX..XX.X........... 13 13
PC1ON XXX.....X........XXXXXXX.X..X........... 13 13
CS1 XXX.....X............................... 4 4
CS_U XXX.....XX.......XXXXXX..X..X........... 13 13
CSA2 XXX....XX........XXXXXX..X..X........... 13 13
ALMR ..............XXX....................... 3 3
CLK ...X.................................... 1 1
CSA1 XXX...X.X........XXXXXX..X..X........... 13 13
INT0 ..........X............................. 1 1
CLR1 XXX..X..X........XXXXXX..X..X........... 13 13
CLR0 XXX.X...X........XXXXXX..X..X........... 13 13
REL0 XXX.....X........XXXXXX.XX..X........... 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 36/0
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 41 I/O I
XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT
1 0 0 4 FB3_2 STD 32 I/O I
XLXN_8<7> 2 0 0 3 FB3_3 STD 49 I/O I
XLXN_8<6> 2 0 0 3 FB3_4 STD 50 I/O I
XLXN_8<5> 2 0 0 3 FB3_5 STD 35 I/O I
XLXN_8<4> 2 0 0 3 FB3_6 STD 53 I/O I
XLXN_8<1> 2 0 0 3 FB3_7 STD 54 I/O I
XLXN_8<0> 2 0 0 3 FB3_8 STD 37 I/O I
SPDB2 4 0 0 1 FB3_9 STD 42 I/O O
SPD2A 4 0 0 1 FB3_10 STD 60 I/O O
XLXI_57/Q41<3> 4 0 0 1 FB3_11 STD 52 I/O I
XLXI_57/Q41<2> 4 0 0 1 FB3_12 STD 61 I/O I
XLXI_57/Q41<1> 4 0 0 1 FB3_13 STD 63 I/O I
XLXI_57/Q41<0> 4 0 0 1 FB3_14 STD 55 I/O I
D<7>_BUFR 4 0 0 1 FB3_15 STD 56 I/O I
D<5>_BUFR 4 0 0 1 FB3_16 STD 65 I/O I
M2PS 4 0 0 1 FB3_17 STD 58 I/O O
SPDB1 4 0 0 1 FB3_18 STD 59 I/O O
Signals Used by Logic in Function Block
1: A0 13: MR_1<7> 25: SPDB1_OBUF.FBK.LFBK
2: A1 14: MR_2<5> 26: SPDB2_OBUF.FBK.LFBK
3: A2 15: MR_2<7> 27: WR
4: CLR1 16: D<0>.PIN 28: XLXI_57/Q41<0>.FBK.LFBK
5: CS 17: D<1>.PIN 29: XLXI_57/Q41<1>.FBK.LFBK
6: M2PS_OBUF.FBK.LFBK
18: D<2>.PIN 30: XLXI_57/Q41<2>.FBK.LFBK
7: MA1 19: D<3>.PIN 31: XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT.FBK.LFBK
8: MB1 20: D<4>.PIN 32: XLXI_57/Q41<3>.FBK.LFBK
9: MC1 21: D<7>.PIN 33: XLXI_57/Q4<0>
10: MR_0<5> 22: RD 34: XLXI_57/Q4<1>
11: MR_0<7> 23: RESET 35: XLXN_8<5>.FBK.LFBK
12: MR_1<5> 24: SPD2A_OBUF.FBK.LFBK
36: XLXN_8<7>.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT
......XXX............................... 3 3
XLXN_8<7> .....................X.........X........ 2 2
XLXN_8<6> .....................X.......X.......... 2 2
XLXN_8<5> .....................X......X........... 2 2
XLXN_8<4> .....................X.....X............ 2 2
XLXN_8<1> .....................X...........X...... 2 2
XLXN_8<0> .....................X..........X....... 2 2
SPDB2 XXX.X..........XXXXXX.X..XX............. 13 13
SPD2A XXX.X..........XXXXXX.XX..X............. 13 13
XLXI_57/Q41<3> ...X..XX......................XX........ 5 5
XLXI_57/Q41<2> ...X..XX...................XX.X......... 6 6
XLXI_57/Q41<1> ...X..XX...................X..X......... 5 5
XLXI_57/Q41<0> ...X..XX......................X......... 4 4
D<7>_BUFR XX........X.X.X....................X.... 6 6
D<5>_BUFR XX.......X.X.X....................X..... 6 6
M2PS XXX.XX.........XXXXXX.X...X............. 13 13
SPDB1 XXX.X..........XXXXXX.X.X.X............. 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 36/0
Number of signals used by logic mapping into function block: 36
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 66 I/O I
(unused) 0 0 0 5 FB4_2 64 I/O I
(unused) 0 0 0 5 FB4_3 71 I/O I
(unused) 0 0 0 5 FB4_4 72 I/O I
(unused) 0 0 0 5 FB4_5 67 I/O I
(unused) 0 0 0 5 FB4_6 76 I/O I
XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT
1 0 0 4 FB4_7 STD 77 I/O I
XLXN_8<3> 2 0 0 3 FB4_8 STD 68 I/O I
XLXN_8<2> 2 0 0 3 FB4_9 STD 70 I/O I
XLXI_57/Q4<3> 4 0 0 1 FB4_10 STD 81 I/O I
XLXI_57/Q4<2> 4 0 0 1 FB4_11 STD 74 I/O I
XLXI_57/Q4<1> 4 0 0 1 FB4_12 STD 82 I/O I
XLXI_57/Q4<0> 4 0 0 1 FB4_13 STD 85 I/O I
D<6>_BUFR 4 0 0 1 FB4_14 STD 78 I/O I
D<4>_BUFR 4 0 0 1 FB4_15 STD 89 I/O I
D<3>_BUFR 4 0 0 1 FB4_16 STD 86 I/O I
SEN0 4 0 0 1 FB4_17 STD 90 I/O O
PC2ON 4 0 0 1 FB4_18 STD 79 I/O O
Signals Used by Logic in Function Block
1: A0 13: MR_1<4> 25: RD
2: A1 14: MR_1<6> 26: RESET
3: A2 15: MR_2<3> 27: SEN0_OBUF.FBK.LFBK
4: CLR0 16: MR_2<4> 28: WR
5: CS 17: MR_2<6> 29: XLXI_57/Q4<0>.FBK.LFBK
6: MA0 18: D<0>.PIN 30: XLXI_57/Q4<1>.FBK.LFBK
7: MB0 19: D<1>.PIN 31: XLXI_57/Q4<2>.FBK.LFBK
8: MC0 20: D<2>.PIN 32: XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK
9: MR_0<3> 21: D<3>.PIN 33: XLXI_57/Q4<3>.FBK.LFBK
10: MR_0<4> 22: D<4>.PIN 34: XLXN_8<3>.FBK.LFBK
11: MR_0<6> 23: D<7>.PIN 35: XLXN_8<4>
12: MR_1<3> 24: PC2ON_OBUF.FBK.LFBK
36: XLXN_8<6>
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT
.....XXX................................ 3 3
XLXN_8<3> ........................X.......X....... 2 2
XLXN_8<2> ........................X.....X......... 2 2
XLXI_57/Q4<3> ...X.XX........................XX....... 5 5
XLXI_57/Q4<2> ...X.XX.....................XX.X........ 6 6
XLXI_57/Q4<1> ...X.XX.....................X..X........ 5 5
XLXI_57/Q4<0> ...X.XX........................X........ 4 4
D<6>_BUFR XX........X..X..X..................X.... 6 6
D<4>_BUFR XX.......X..X..X..................X..... 6 6
D<3>_BUFR XX......X..X..X..................X...... 6 6
SEN0 XXX.X............XXXXXX..XXX............ 13 13
PC2ON XXX.X............XXXXXXX.X.X............ 13 13
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
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