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来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 934 行 · 第 1/4 页
RPT
934 行
cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: top Date: 4-26-2006, 9:26AM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
57 /72 ( 79%) 186 /360 ( 52%) 37 /72 ( 51%) 68 /72 ( 94%) 136/144 ( 94%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 39 39 | I/O : 64 2
Output : 23 23 | GCK/IO : 3 0
Bidirectional : 6 6 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 68 68
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 37
Non-registered Macrocell driving I/O 13
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 57 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 57 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
Buffering output signal D<7> to allow all signals assigned to this function
block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
Buffering output signal D<6> to allow all signals assigned to this function
block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
Buffering output signal D<5> to allow all signals assigned to this function
block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
Buffering output signal D<4> to allow all signals assigned to this function
block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
Buffering output signal D<3> to allow all signals assigned to this function
block to be placed.
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
ALMR 1 3 FB2_12 STD SLOW 6 I/O O
CLK 1 1 FB2_13 STD SLOW 8 I/O O
CLR0 4 13 FB2_17 STD 12 I/O I RESET
CLR1 4 13 FB2_16 STD 10 I/O I RESET
CS1 1 4 FB2_8 STD SLOW 97 I/O O
CSA1 4 13 FB2_14 STD 9 I/O I RESET
CSA2 4 13 FB2_11 STD 4 GTS/I/O (b) RESET
CS_U 4 13 FB2_10 STD 1 I/O (b) RESET
D<0> 5 8 FB1_1 STD SLOW 16 I/O I/O
D<1> 5 8 FB1_2 STD SLOW 13 I/O I/O
D<2> 5 8 FB1_3 STD SLOW 18 I/O I/O
D<3> 2 3 FB1_4 STD SLOW 20 I/O I/O
D<3>_BUFR 4 6 FB4_16 STD 86 I/O I
D<4> 2 3 FB1_5 STD SLOW 14 I/O I/O
D<4>_BUFR 4 6 FB4_15 STD 89 I/O I
D<5> 2 3 FB1_6 STD SLOW 15 I/O O
D<5>_BUFR 4 6 FB3_16 STD 65 I/O I
D<6> 2 3 FB1_7 STD SLOW 25 I/O O
D<6>_BUFR 4 6 FB4_14 STD 78 I/O I
D<7> 2 3 FB1_8 STD SLOW 17 I/O I/O
D<7>_BUFR 4 6 FB3_15 STD 56 I/O I
INT0 1 1 FB2_15 STD SLOW 11 I/O O
M1CLR 4 13 FB2_4 STD SLOW 93 I/O O RESET
M1PS 4 13 FB2_1 STD SLOW 87 I/O O RESET
M1SG 4 13 FB2_3 STD SLOW 91 I/O O RESET
M2CLR 4 13 FB1_16 STD SLOW 39 I/O O RESET
M2PS 4 13 FB3_17 STD SLOW 58 I/O O RESET
M2SG 4 13 FB1_18 STD SLOW 40 I/O O RESET
PC1ON 4 13 FB2_6 STD SLOW 96 I/O O RESET
PC2ON 4 13 FB4_18 STD SLOW 79 I/O O RESET
REL0 4 13 FB2_18 STD SLOW 92 I/O O RESET
SEN0 4 13 FB4_17 STD SLOW 90 I/O O RESET
SEN1 4 13 FB2_5 STD SLOW 95 I/O O RESET
SEN2 4 13 FB1_13 STD SLOW 36 I/O O RESET
SPD2A 4 13 FB3_10 STD SLOW 60 I/O O RESET
SPDA1 4 13 FB2_2 STD SLOW 94 I/O O RESET
SPDB1 4 13 FB3_18 STD SLOW 59 I/O O RESET
SPDB2 4 13 FB3_9 STD SLOW 42 I/O O RESET
UART0 3 6 FB1_17 STD SLOW 30 I/O O
XLXI_57/Q41<0> 4 4 FB3_14 STD 55 I/O I RESET
XLXI_57/Q41<1> 4 5 FB3_13 STD 63 I/O I RESET
XLXI_57/Q41<2> 4 6 FB3_12 STD 61 I/O I RESET
XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT 1 3 FB3_2 STD 32 I/O I
XLXI_57/Q41<3> 4 5 FB3_11 STD 52 I/O I RESET
XLXI_57/Q4<0> 4 4 FB4_13 STD 85 I/O I RESET
XLXI_57/Q4<1> 4 5 FB4_12 STD 82 I/O I RESET
XLXI_57/Q4<2> 4 6 FB4_11 STD 74 I/O I RESET
XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT 1 3 FB4_7 STD 77 I/O I
XLXI_57/Q4<3> 4 5 FB4_10 STD 81 I/O I RESET
XLXN_8<0> 2 2 FB3_8 STD 37 I/O I RESET
XLXN_8<1> 2 2 FB3_7 STD 54 I/O I RESET
XLXN_8<2> 2 2 FB4_9 STD 70 I/O I RESET
XLXN_8<3> 2 2 FB4_8 STD 68 I/O I RESET
XLXN_8<4> 2 2 FB3_6 STD 53 I/O I RESET
XLXN_8<5> 2 2 FB3_5 STD 35 I/O I RESET
XLXN_8<6> 2 2 FB3_4 STD 50 I/O I RESET
XLXN_8<7> 2 2 FB3_3 STD 49 I/O I RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
A0 FB2_17 12 I/O I
A1 FB1_14 27 GCK/I/O I
A2 FB1_15 29 I/O I
CLK8 FB1_9 22 GCK/I/O I
CS FB1_10 28 I/O I
INT_L0 FB2_16 10 I/O I
MA0 FB3_16 65 I/O I
MA1 FB3_13 63 I/O I
MB0 FB3_15 56 I/O I
MB1 FB3_12 61 I/O I
MC0 FB3_14 55 I/O I
MC1 FB3_11 52 I/O I
MR_0<0> FB4_9 70 I/O I
MR_0<1> FB4_10 81 I/O I
MR_0<2> FB4_11 74 I/O I
MR_0<3> FB4_12 82 I/O I
MR_0<4> FB4_13 85 I/O I
MR_0<5> FB4_14 78 I/O I
MR_0<6> FB4_15 89 I/O I
MR_0<7> FB4_16 86 I/O I
MR_1<0> FB4_1 66 I/O I
MR_1<1> FB4_2 64 I/O I
MR_1<2> FB4_3 71 I/O I
MR_1<3> FB4_4 72 I/O I
MR_1<4> FB4_5 67 I/O I
MR_1<5> FB4_6 76 I/O I
MR_1<6> FB4_7 77 I/O I
MR_1<7> FB4_8 68 I/O I
MR_2<0> FB3_8 37 I/O I
MR_2<1> FB3_7 54 I/O I
MR_2<2> FB3_6 53 I/O I
MR_2<3> FB3_5 35 I/O I
MR_2<4> FB3_4 50 I/O I
MR_2<5> FB3_3 49 I/O I
MR_2<6> FB3_2 32 I/O I
MR_2<7> FB3_1 41 I/O I
RD FB1_11 23 GCK/I/O I
RESET FB2_9 99 GSR/I/O I
WR FB2_14 9 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 12 35 35 40 6/6 18
FB2 16 29 29 52 11/0 18
FB3 17 36 36 53 4/0 18
FB4 12 36 36 41 2/0 18
---- ----- ----- -----
57 186 23/6 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 35/1
Number of signals used by logic mapping into function block: 35
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
D<0> 5 0 0 0 FB1_1 STD 16 I/O I/O
D<1> 5 0 0 0 FB1_2 STD 13 I/O I/O
D<2> 5 0 0 0 FB1_3 STD 18 I/O I/O
D<3> 2 0 0 3 FB1_4 STD 20 I/O I/O
D<4> 2 0 0 3 FB1_5 STD 14 I/O I/O
D<5> 2 0 0 3 FB1_6 STD 15 I/O O
D<6> 2 0 0 3 FB1_7 STD 25 I/O O
D<7> 2 0 0 3 FB1_8 STD 17 I/O I/O
(unused) 0 0 0 5 FB1_9 22 GCK/I/O I
(unused) 0 0 0 5 FB1_10 28 I/O I
(unused) 0 0 0 5 FB1_11 23 GCK/I/O I
(unused) 0 0 0 5 FB1_12 33 I/O
SEN2 4 0 0 1 FB1_13 STD 36 I/O O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O I
(unused) 0 0 0 5 FB1_15 29 I/O I
M2CLR 4 0 0 1 FB1_16 STD 39 I/O O
UART0 3 0 0 2 FB1_17 STD 30 I/O O
M2SG 4 0 0 1 FB1_18 STD 40 I/O O
Signals Used by Logic in Function Block
1: A0 13: M2CLR_OBUF.FBK.LFBK
25: D<1>.PIN
2: A1 14: M2SG_OBUF.FBK.LFBK
26: D<2>.PIN
3: A2 15: MR_0<0> 27: D<3>.PIN
4: CSA1 16: MR_0<1> 28: D<4>.PIN
5: CSA2 17: MR_0<2> 29: D<7>.PIN
6: CS 18: MR_1<0> 30: RESET
7: CS_U 19: MR_1<1> 31: SEN2_OBUF.FBK.LFBK
8: D<3>_BUFR 20: MR_1<2> 32: WR
9: D<4>_BUFR 21: MR_2<0> 33: XLXN_8<0>
10: D<5>_BUFR 22: MR_2<1> 34: XLXN_8<1>
11: D<6>_BUFR 23: MR_2<2> 35: XLXN_8<2>
12: D<7>_BUFR 24: D<0>.PIN
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
D<0> XXX..X........X..X..X...........X....... 8 8
D<1> XXX..X.........X..X..X...........X...... 8 8
D<2> XXX..X..........X..X..X...........X..... 8 8
D<3> ..X..X.X................................ 3 3
D<4> ..X..X..X............................... 3 3
D<5> ..X..X...X.............................. 3 3
D<6> ..X..X....X............................. 3 3
D<7> ..X..X.....X............................ 3 3
SEN2 XXX..X.................XXXXXXXXX........ 13 13
M2CLR XXX..X......X..........XXXXXXX.X........ 13 13
UART0 ...XX.X.............XXX................. 6 6
M2SG XXX..X.......X.........XXXXXXX.X........ 13 13
0----+----1----+----2----+----3----+----4
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