count4.vhdl

xilinx xc9572 cpld 实现的伺服电机控制器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity count4 is
    Port ( CE :  in std_logic;
           CLR : in std_logic;
           UP : in std_logic_vector(1 downto 0);
           CCLK : in std_logic;
           Qout : out std_logic_vector(3 downto 0));
end count4;

architecture Behavioral of count4 is
 signal Temp:std_logic_vector(2 downto 0);
 signal dir:std_logic;
 begin
    
	process(CCLK,CLR,UP,CE)
	 begin
	 if(CLR='1') then
	    Temp<=(others=>'0');
		 dir<='0'; 	
	 elsif (CCLK'event and CCLK='1') then
		if(CE='0') then
		  if(UP="01") then
		    dir<='0';
			 Temp<= Temp+1;
		  elsif(UP="10") then
		    Temp<= Temp-1; 	 
		  	 dir<='1';
		  else
		    Temp<=Temp;
		  end if;
	   end if;
	  end if;
	 end process;
 	 Qout<=dir & temp;

end Behavioral;