testadd.syr

xilinx xc9572 cpld 实现的伺服电机控制器

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.67 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.67 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: testadd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : testadd.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : testadd
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Top Module Name                    : testadd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : ONLY
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : testadd.lso
verilog2001                        : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/FPGA/TEST/xc9572/testadd.vhf in Library work.
Entity <ADSU1_MXILINX_testadd> (Architecture <BEHAVIORAL>) compiled.
ERROR:HDLParsers:164 - D:/FPGA/TEST/xc9572/testadd.vhf Line 217. parse error, unexpected CLOSEPAR, expecting IDENTIFIER
--> 

Total memory usage is 48644 kilobytes