mdecode.mfd

xilinx xc9572 cpld 实现的伺服电机控制器

MDF Database:  version 1.0
MDF_INFO | mdecode | XC9572-10-TQ100
MACROCELL | 0 | 17 | Q41<0>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 3 | 2 | 9 | 0 | 16 | 0 | 15
INPUTS | 4 | MA1  | MB1  | CLR1  | Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK
INPUTMC | 1 | 0 | 8
INPUTP | 3 | 87 | 50 | 12
EQ | 4 | 
   Q41<0>.T = MA1 & !MB1
	# !MA1 & MB1;
   Q41<0>.CLK = !Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK;
   Q41<0>.AR = CLR1;

MACROCELL | 0 | 13 | Q4<0>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 3 | 2 | 1 | 0 | 12 | 0 | 11
INPUTS | 4 | MA0  | MB0  | CLR0  | Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK
INPUTMC | 1 | 0 | 7
INPUTP | 3 | 9 | 67 | 62
EQ | 4 | 
   Q4<0>.T = MA0 & !MB0
	# !MA0 & MB0;
   Q4<0>.CLK = !Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK;
   Q4<0>.AR = CLR0;

MACROCELL | 0 | 16 | Q41<1>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 0 | 15 | 0 | 1
INPUTS | 5 | Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK  | MA1  | MB1  | CLR1  | Q41<0>.FBK.LFBK
INPUTMC | 2 | 0 | 8 | 0 | 17
INPUTP | 3 | 87 | 50 | 12
EQ | 4 | 
   Q41<1>.T = MA1 & !MB1 & Q41<0>.FBK.LFBK
	# !MA1 & MB1 & !Q41<0>.FBK.LFBK;
   Q41<1>.CLK = !Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK;
   Q41<1>.AR = CLR1;

MACROCELL | 0 | 12 | Q4<1>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 3 | 1 | 0 | 11
INPUTS | 5 | Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK  | MA0  | MB0  | CLR0  | Q4<0>.FBK.LFBK
INPUTMC | 2 | 0 | 7 | 0 | 13
INPUTP | 3 | 9 | 67 | 62
EQ | 4 | 
   Q4<1>.T = MA0 & !MB0 & Q4<0>.FBK.LFBK
	# !MA0 & MB0 & !Q4<0>.FBK.LFBK;
   Q4<1>.CLK = !Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK;
   Q4<1>.AR = CLR0;

MACROCELL | 0 | 15 | Q41<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 1 | 3 | 9
INPUTS | 6 | Q41<1>.FBK.LFBK  | Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK  | MA1  | MB1  | CLR1  | Q41<0>.FBK.LFBK
INPUTMC | 3 | 0 | 16 | 0 | 8 | 0 | 17
INPUTP | 3 | 87 | 50 | 12
EQ | 4 | 
   Q41<2>.T = MA1 & !MB1 & Q41<0>.FBK.LFBK & Q41<1>.FBK.LFBK
	# !MA1 & MB1 & !Q41<0>.FBK.LFBK & !Q41<1>.FBK.LFBK;
   Q41<2>.CLK = !Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK;
   Q41<2>.AR = CLR1;

MACROCELL | 0 | 11 | Q4<2>
ATTRIBUTES | 4326192 | 0
OUTPUTMC | 1 | 1 | 1
INPUTS | 6 | Q4<1>.FBK.LFBK  | Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK  | MA0  | MB0  | CLR0  | Q4<0>.FBK.LFBK
INPUTMC | 3 | 0 | 12 | 0 | 7 | 0 | 13
INPUTP | 3 | 9 | 67 | 62
EQ | 4 | 
   Q4<2>.T = MA0 & !MB0 & Q4<0>.FBK.LFBK & Q4<1>.FBK.LFBK
	# !MA0 & MB0 & !Q4<0>.FBK.LFBK & !Q4<1>.FBK.LFBK;
   Q4<2>.CLK = !Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK;
   Q4<2>.AR = CLR0;

MACROCELL | 0 | 14 | Q41<3>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 0 | 14 | 0 | 9
INPUTS | 5 | Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK  | MA1  | MB1  | CLR1  | Q41<3>.FBK.LFBK
INPUTMC | 2 | 0 | 8 | 0 | 14
INPUTP | 3 | 87 | 50 | 12
EQ | 4 | 
   Q41<3>.T = MA1 & !MB1 & Q41<3>.FBK.LFBK
	# !MA1 & MB1 & !Q41<3>.FBK.LFBK;
   Q41<3>.CLK = !Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK;
   Q41<3>.AR = CLR1;

MACROCELL | 0 | 10 | Q4<3>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 1 | 11 | 0 | 10
INPUTS | 5 | Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK  | MA0  | MB0  | CLR0  | Q4<3>.FBK.LFBK
INPUTMC | 2 | 0 | 7 | 0 | 10
INPUTP | 3 | 9 | 67 | 62
EQ | 4 | 
   Q4<3>.T = MA0 & !MB0 & Q4<3>.FBK.LFBK
	# !MA0 & MB0 & !Q4<3>.FBK.LFBK;
   Q4<3>.CLK = !Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK;
   Q4<3>.AR = CLR0;

MACROCELL | 2 | 1 | O_0
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | Q4<0>  | RD
INPUTMC | 1 | 0 | 13
INPUTP | 1 | 89
EQ | 4 | 
   O<0>.D = Gnd;
   O<0>.CLK = Gnd;
   O<0>.AP = Q4<0> & !RD;
   O<0>.AR = !Q4<0> & !RD;

MACROCELL | 3 | 1 | O_1
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | Q4<1>  | RD
INPUTMC | 1 | 0 | 12
INPUTP | 1 | 89
EQ | 4 | 
   O<1>.D = Gnd;
   O<1>.CLK = Gnd;
   O<1>.AP = Q4<1> & !RD;
   O<1>.AR = !Q4<1> & !RD;

MACROCELL | 1 | 1 | O_2
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | Q4<2>  | RD
INPUTMC | 1 | 0 | 11
INPUTP | 1 | 89
EQ | 4 | 
   O<2>.D = Gnd;
   O<2>.CLK = Gnd;
   O<2>.AP = Q4<2> & !RD;
   O<2>.AR = !Q4<2> & !RD;

MACROCELL | 1 | 11 | O_3
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | Q4<3>  | RD
INPUTMC | 1 | 0 | 10
INPUTP | 1 | 89
EQ | 4 | 
   O<3>.D = Gnd;
   O<3>.CLK = Gnd;
   O<3>.AP = Q4<3> & !RD;
   O<3>.AR = !Q4<3> & !RD;

MACROCELL | 2 | 9 | O_4
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | Q41<0>  | RD
INPUTMC | 1 | 0 | 17
INPUTP | 1 | 89
EQ | 4 | 
   O<4>.D = Gnd;
   O<4>.CLK = Gnd;
   O<4>.AP = Q41<0> & !RD;
   O<4>.AR = !Q41<0> & !RD;

MACROCELL | 0 | 1 | O_5
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | RD  | Q41<1>.FBK.LFBK
INPUTMC | 1 | 0 | 16
INPUTP | 1 | 89
EQ | 4 | 
   O<5>.D = Gnd;
   O<5>.CLK = Gnd;
   O<5>.AP = !RD & Q41<1>.FBK.LFBK;
   O<5>.AR = !RD & !Q41<1>.FBK.LFBK;

MACROCELL | 3 | 9 | O_6
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | Q41<2>  | RD
INPUTMC | 1 | 0 | 15
INPUTP | 1 | 89
EQ | 4 | 
   O<6>.D = Gnd;
   O<6>.CLK = Gnd;
   O<6>.AP = Q41<2> & !RD;
   O<6>.AR = !Q41<2> & !RD;

MACROCELL | 0 | 9 | O_7
ATTRIBUTES | 8651696 | 0
INPUTS | 2 | RD  | Q41<3>.FBK.LFBK
INPUTMC | 1 | 0 | 14
INPUTP | 1 | 89
EQ | 4 | 
   O<7>.D = Gnd;
   O<7>.CLK = Gnd;
   O<7>.AP = !RD & Q41<3>.FBK.LFBK;
   O<7>.AR = !RD & !Q41<3>.FBK.LFBK;

MACROCELL | 0 | 8 | Q41<2>/Q41<2>_CLKF__$INT
ATTRIBUTES | 199424 | 0
OUTPUTMC | 4 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14
INPUTS | 3 | MA1  | MB1  | MC1
INPUTP | 3 | 87 | 50 | 26
EQ | 1 | 
   Q41<2>/Q41<2>_CLKF__$INT = MA1 & MB1 & !MC1;

MACROCELL | 0 | 7 | Q4<2>/Q4<2>_CLKF__$INT
ATTRIBUTES | 199424 | 0
OUTPUTMC | 4 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10
INPUTS | 3 | MA0  | MB0  | MC0
INPUTP | 3 | 9 | 67 | 15
EQ | 1 | 
   Q4<2>/Q4<2>_CLKF__$INT = MA0 & MB0 & !MC0;

PIN | CLR1 | 64 | 0 | N/A | 12 | 4 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14
PIN | MA1 | 64 | 0 | N/A | 87 | 5 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 8
PIN | MB1 | 64 | 0 | N/A | 50 | 5 | 0 | 17 | 0 | 16 | 0 | 15 | 0 | 14 | 0 | 8
PIN | CLR0 | 64 | 0 | N/A | 62 | 4 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10
PIN | MA0 | 64 | 0 | N/A | 9 | 5 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7
PIN | MB0 | 64 | 0 | N/A | 67 | 5 | 0 | 13 | 0 | 12 | 0 | 11 | 0 | 10 | 0 | 7
PIN | MC0 | 64 | 0 | N/A | 15 | 1 | 0 | 7
PIN | MC1 | 64 | 0 | N/A | 26 | 1 | 0 | 8
PIN | RD | 64 | 0 | N/A | 89 | 8 | 2 | 1 | 3 | 1 | 1 | 1 | 1 | 11 | 2 | 9 | 0 | 1 | 3 | 9 | 0 | 9
PIN | O<0> | 128 | 0 | N/A | 29
PIN | O<1> | 128 | 0 | N/A | 58
PIN | O<2> | 128 | 0 | N/A | 86
PIN | O<3> | 128 | 0 | N/A | 5
PIN | O<4> | 128 | 0 | N/A | 54
PIN | O<5> | 128 | 0 | N/A | 11
PIN | O<6> | 128 | 0 | N/A | 73
PIN | O<7> | 128 | 0 | N/A | 25