sel4_1_timesim.nlf

xilinx xc9572 cpld 实现的伺服电机控制器

Release 6.3i - netgen G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Reading design sel4_1.nga ...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist sel4_1_timesim.vhd ...
Writing VHDL SDF file sel4_1_timesim.sdf ...
Total memory usage is 36068 kilobytes