d5_32e.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_1076_7
-- /___/   /\     Timestamp : 04/03/2006 14:12:12
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: d5_32e
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity d5_32e is
   port ( A0         : in    std_logic; 
          A1         : in    std_logic; 
          A2         : in    std_logic; 
          A3         : in    std_logic; 
          A4         : in    std_logic;
			 E          : in    std_logic; 
          Dout       : out   std_logic_vector(23 downto 0));
end d5_32e;

architecture BEHAVIORAL of d5_32e is
signal  addr: std_logic_vector (4 downto 0);
begin
  addr<=A4 & A3 & A2 & A1 & A0;
  process(addr,E) 
  begin
  if(E='1') then
    Dout<="000000000000000000000000";
  else
    case addr  is
	  when  "00000"=> Dout<="000000000000000000000001";	 
	  when  "00001"=> Dout<="000000000000000000000010";
	  when  "00010"=> Dout<="000000000000000000000100";
	  when  "00011"=> Dout<="000000000000000000001000";
	  when  "00100"=> Dout<="000000000000000000010000";
	  when  "00101"=> Dout<="000000000000000000100000";
	  when  "00110"=> Dout<="000000000000000001000000";
	  when  "00111"=> Dout<="000000000000000010000000";
	  when  "01000"=> Dout<="000000000000000100000000";	 
	  when  "01001"=> Dout<="000000000000001000000000";
	  when  "01010"=> Dout<="000000000000010000000000";
	  when  "01011"=> Dout<="000000000000100000000000";
	  when  "01100"=> Dout<="000000000001000000000000";
	  when  "01101"=> Dout<="000000000010000000000000";
	  when  "01110"=> Dout<="000000000100000000000000";
	  when  "01111"=> Dout<="000000001000000000000000";
	  when  "10000"=> Dout<="000000010000000000000000";	 
	  when  "10001"=> Dout<="000000100000000000000000";
	  when  "10010"=> Dout<="000001000000000000000000";
	  when  "10011"=> Dout<="000010000000000000000000";
	  when  "10100"=> Dout<="000100000000000000000000";
	  when  "10101"=> Dout<="001000000000000000000000";
	  when  "10110"=> Dout<="010000000000000000000000";
	  when  "10111"=> Dout<="100000000000000000000000";
     when   others=> Dout<="000000000000000000000000";
	 end case; 
  end if;
  end  process;

end BEHAVIORAL;

-- synopsys translate_off
configuration CFG_d5_32e of  d5_32e is
   for BEHAVIORAL
   end for;
end CFG_d5_32e;
-- synopsys translate_on