sel4_1_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

      O => DO_5_OBUFE_D2_PT_1
    );
  DO_5_OBUFE_D2_PT_2_103 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_5_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_5_IBUF,
      O => DO_5_OBUFE_D2_PT_2
    );
  DO_5_OBUFE_D2_PT_3_104 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_5_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_5_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_5_IBUF,
      O => DO_5_OBUFE_D2_PT_3
    );
  DO_5_OBUFE_D2_105 : X_OR4
    port map (
      I0 => DO_5_OBUFE_D2_PT_0,
      I1 => DO_5_OBUFE_D2_PT_1,
      I2 => DO_5_OBUFE_D2_PT_2,
      I3 => DO_5_OBUFE_D2_PT_3,
      O => DO_5_OBUFE_D2
    );
  DO_5_OBUFE_TRST_106 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_5_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_5_OBUFE_TRST_IN1,
      O => DO_5_OBUFE_TRST
    );
  DO_6_OBUFE_107 : X_BUF
    port map (
      I => DO_6_OBUFE_Q,
      O => DO_6_OBUFE
    );
  DO_6_OBUFE_OE_108 : X_BUF
    port map (
      I => DO_6_OBUFE_BUFOE_OUT,
      O => DO_6_OBUFE_OE
    );
  DO_6_OBUFE_BUFOE_OUT_109 : X_BUF
    port map (
      I => DO_6_OBUFE_TRST,
      O => DO_6_OBUFE_BUFOE_OUT
    );
  DO_6_OBUFE_Q_110 : X_BUF
    port map (
      I => DO_6_OBUFE_D,
      O => DO_6_OBUFE_Q
    );
  DO_6_OBUFE_D_111 : X_XOR2
    port map (
      I0 => DO_6_OBUFE_D1,
      I1 => DO_6_OBUFE_D2,
      O => DO_6_OBUFE_D
    );
  DO_6_OBUFE_D1_112 : X_ZERO
    port map (
      O => DO_6_OBUFE_D1
    );
  DO_6_OBUFE_D2_PT_0_113 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_6_IBUF,
      O => DO_6_OBUFE_D2_PT_0
    );
  DO_6_OBUFE_D2_PT_1_114 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_6_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_6_IBUF,
      O => DO_6_OBUFE_D2_PT_1
    );
  DO_6_OBUFE_D2_PT_2_115 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_6_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_6_IBUF,
      O => DO_6_OBUFE_D2_PT_2
    );
  DO_6_OBUFE_D2_PT_3_116 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_6_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_6_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_6_IBUF,
      O => DO_6_OBUFE_D2_PT_3
    );
  DO_6_OBUFE_D2_117 : X_OR4
    port map (
      I0 => DO_6_OBUFE_D2_PT_0,
      I1 => DO_6_OBUFE_D2_PT_1,
      I2 => DO_6_OBUFE_D2_PT_2,
      I3 => DO_6_OBUFE_D2_PT_3,
      O => DO_6_OBUFE_D2
    );
  DO_6_OBUFE_TRST_118 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_6_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_6_OBUFE_TRST_IN1,
      O => DO_6_OBUFE_TRST
    );
  DO_7_OBUFE_119 : X_BUF
    port map (
      I => DO_7_OBUFE_Q,
      O => DO_7_OBUFE
    );
  DO_7_OBUFE_OE_120 : X_BUF
    port map (
      I => DO_7_OBUFE_BUFOE_OUT,
      O => DO_7_OBUFE_OE
    );
  DO_7_OBUFE_BUFOE_OUT_121 : X_BUF
    port map (
      I => DO_7_OBUFE_TRST,
      O => DO_7_OBUFE_BUFOE_OUT
    );
  DO_7_OBUFE_Q_122 : X_BUF
    port map (
      I => DO_7_OBUFE_D,
      O => DO_7_OBUFE_Q
    );
  DO_7_OBUFE_D_123 : X_XOR2
    port map (
      I0 => DO_7_OBUFE_D1,
      I1 => DO_7_OBUFE_D2,
      O => DO_7_OBUFE_D
    );
  DO_7_OBUFE_D1_124 : X_ZERO
    port map (
      O => DO_7_OBUFE_D1
    );
  DO_7_OBUFE_D2_PT_0_125 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_7_IBUF,
      O => DO_7_OBUFE_D2_PT_0
    );
  DO_7_OBUFE_D2_PT_1_126 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_7_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_7_IBUF,
      O => DO_7_OBUFE_D2_PT_1
    );
  DO_7_OBUFE_D2_PT_2_127 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_7_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_7_IBUF,
      O => DO_7_OBUFE_D2_PT_2
    );
  DO_7_OBUFE_D2_PT_3_128 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_7_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_7_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_7_IBUF,
      O => DO_7_OBUFE_D2_PT_3
    );
  DO_7_OBUFE_D2_129 : X_OR4
    port map (
      I0 => DO_7_OBUFE_D2_PT_0,
      I1 => DO_7_OBUFE_D2_PT_1,
      I2 => DO_7_OBUFE_D2_PT_2,
      I3 => DO_7_OBUFE_D2_PT_3,
      O => DO_7_OBUFE_D2
    );
  DO_7_OBUFE_TRST_130 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_7_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_7_OBUFE_TRST_IN1,
      O => DO_7_OBUFE_TRST
    );
  NlwInverterBlock_DO_0_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_0_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_0_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_0_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_0_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_0_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_0_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_0_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_0_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_0_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_0_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_0_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_1_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_1_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_1_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_1_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_1_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_1_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_1_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_1_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_1_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_1_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_1_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_1_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_2_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_2_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_2_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_2_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_2_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_2_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_2_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_2_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_2_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_2_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_2_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_2_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_3_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_3_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_3_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_3_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_3_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_3_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_3_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_3_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_3_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_3_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_3_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_3_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_4_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_4_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_4_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_4_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_4_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_4_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_4_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_4_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_4_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_4_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_4_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_4_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_5_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_5_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_5_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_5_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_5_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_5_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_5_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_5_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_5_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_5_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_5_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_5_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_6_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_6_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_6_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_6_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_6_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_6_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_6_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_6_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_6_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_6_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_6_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_6_OBUFE_TRST_IN1
    );
  NlwInverterBlock_DO_7_OBUFE_D2_PT_1_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_7_OBUFE_D2_PT_1_IN1
    );
  NlwInverterBlock_DO_7_OBUFE_D2_PT_2_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_7_OBUFE_D2_PT_2_IN0
    );
  NlwInverterBlock_DO_7_OBUFE_D2_PT_3_IN0 : X_INV
    port map (
      I => A1_IBUF,
      O => NlwInverterSignal_DO_7_OBUFE_D2_PT_3_IN0
    );
  NlwInverterBlock_DO_7_OBUFE_D2_PT_3_IN1 : X_INV
    port map (
      I => A0_IBUF,
      O => NlwInverterSignal_DO_7_OBUFE_D2_PT_3_IN1
    );
  NlwInverterBlock_DO_7_OBUFE_TRST_IN0 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_7_OBUFE_TRST_IN0
    );
  NlwInverterBlock_DO_7_OBUFE_TRST_IN1 : X_INV
    port map (
      I => CS_IBUF,
      O => NlwInverterSignal_DO_7_OBUFE_TRST_IN1
    );

end Structure;