sel4_1_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

  DO_5_Q : X_TRI
    port map (
      I => DO_5_OBUFE,
      CTL => DO_5_OBUFE_OE,
      O => DO(5)
    );
  DO_6_Q : X_TRI
    port map (
      I => DO_6_OBUFE,
      CTL => DO_6_OBUFE_OE,
      O => DO(6)
    );
  DO_7_Q : X_TRI
    port map (
      I => DO_7_OBUFE,
      CTL => DO_7_OBUFE_OE,
      O => DO(7)
    );
  DO_0_OBUFE_35 : X_BUF
    port map (
      I => DO_0_OBUFE_Q,
      O => DO_0_OBUFE
    );
  DO_0_OBUFE_OE_36 : X_BUF
    port map (
      I => DO_0_OBUFE_BUFOE_OUT,
      O => DO_0_OBUFE_OE
    );
  DO_0_OBUFE_BUFOE_OUT_37 : X_BUF
    port map (
      I => DO_0_OBUFE_TRST,
      O => DO_0_OBUFE_BUFOE_OUT
    );
  DO_0_OBUFE_Q_38 : X_BUF
    port map (
      I => DO_0_OBUFE_D,
      O => DO_0_OBUFE_Q
    );
  DO_0_OBUFE_D_39 : X_XOR2
    port map (
      I0 => DO_0_OBUFE_D1,
      I1 => DO_0_OBUFE_D2,
      O => DO_0_OBUFE_D
    );
  DO_0_OBUFE_D1_40 : X_ZERO
    port map (
      O => DO_0_OBUFE_D1
    );
  DO_0_OBUFE_D2_PT_0_41 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_0_IBUF,
      O => DO_0_OBUFE_D2_PT_0
    );
  DO_0_OBUFE_D2_PT_1_42 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_0_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_0_IBUF,
      O => DO_0_OBUFE_D2_PT_1
    );
  DO_0_OBUFE_D2_PT_2_43 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_0_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_0_IBUF,
      O => DO_0_OBUFE_D2_PT_2
    );
  DO_0_OBUFE_D2_PT_3_44 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_0_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_0_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_0_IBUF,
      O => DO_0_OBUFE_D2_PT_3
    );
  DO_0_OBUFE_D2_45 : X_OR4
    port map (
      I0 => DO_0_OBUFE_D2_PT_0,
      I1 => DO_0_OBUFE_D2_PT_1,
      I2 => DO_0_OBUFE_D2_PT_2,
      I3 => DO_0_OBUFE_D2_PT_3,
      O => DO_0_OBUFE_D2
    );
  DO_0_OBUFE_TRST_46 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_0_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_0_OBUFE_TRST_IN1,
      O => DO_0_OBUFE_TRST
    );
  DO_1_OBUFE_47 : X_BUF
    port map (
      I => DO_1_OBUFE_Q,
      O => DO_1_OBUFE
    );
  DO_1_OBUFE_OE_48 : X_BUF
    port map (
      I => DO_1_OBUFE_BUFOE_OUT,
      O => DO_1_OBUFE_OE
    );
  DO_1_OBUFE_BUFOE_OUT_49 : X_BUF
    port map (
      I => DO_1_OBUFE_TRST,
      O => DO_1_OBUFE_BUFOE_OUT
    );
  DO_1_OBUFE_Q_50 : X_BUF
    port map (
      I => DO_1_OBUFE_D,
      O => DO_1_OBUFE_Q
    );
  DO_1_OBUFE_D_51 : X_XOR2
    port map (
      I0 => DO_1_OBUFE_D1,
      I1 => DO_1_OBUFE_D2,
      O => DO_1_OBUFE_D
    );
  DO_1_OBUFE_D1_52 : X_ZERO
    port map (
      O => DO_1_OBUFE_D1
    );
  DO_1_OBUFE_D2_PT_0_53 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_1_IBUF,
      O => DO_1_OBUFE_D2_PT_0
    );
  DO_1_OBUFE_D2_PT_1_54 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_1_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_1_IBUF,
      O => DO_1_OBUFE_D2_PT_1
    );
  DO_1_OBUFE_D2_PT_2_55 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_1_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_1_IBUF,
      O => DO_1_OBUFE_D2_PT_2
    );
  DO_1_OBUFE_D2_PT_3_56 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_1_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_1_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_1_IBUF,
      O => DO_1_OBUFE_D2_PT_3
    );
  DO_1_OBUFE_D2_57 : X_OR4
    port map (
      I0 => DO_1_OBUFE_D2_PT_0,
      I1 => DO_1_OBUFE_D2_PT_1,
      I2 => DO_1_OBUFE_D2_PT_2,
      I3 => DO_1_OBUFE_D2_PT_3,
      O => DO_1_OBUFE_D2
    );
  DO_1_OBUFE_TRST_58 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_1_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_1_OBUFE_TRST_IN1,
      O => DO_1_OBUFE_TRST
    );
  DO_2_OBUFE_59 : X_BUF
    port map (
      I => DO_2_OBUFE_Q,
      O => DO_2_OBUFE
    );
  DO_2_OBUFE_OE_60 : X_BUF
    port map (
      I => DO_2_OBUFE_BUFOE_OUT,
      O => DO_2_OBUFE_OE
    );
  DO_2_OBUFE_BUFOE_OUT_61 : X_BUF
    port map (
      I => DO_2_OBUFE_TRST,
      O => DO_2_OBUFE_BUFOE_OUT
    );
  DO_2_OBUFE_Q_62 : X_BUF
    port map (
      I => DO_2_OBUFE_D,
      O => DO_2_OBUFE_Q
    );
  DO_2_OBUFE_D_63 : X_XOR2
    port map (
      I0 => DO_2_OBUFE_D1,
      I1 => DO_2_OBUFE_D2,
      O => DO_2_OBUFE_D
    );
  DO_2_OBUFE_D1_64 : X_ZERO
    port map (
      O => DO_2_OBUFE_D1
    );
  DO_2_OBUFE_D2_PT_0_65 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_2_IBUF,
      O => DO_2_OBUFE_D2_PT_0
    );
  DO_2_OBUFE_D2_PT_1_66 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_2_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_2_IBUF,
      O => DO_2_OBUFE_D2_PT_1
    );
  DO_2_OBUFE_D2_PT_2_67 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_2_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_2_IBUF,
      O => DO_2_OBUFE_D2_PT_2
    );
  DO_2_OBUFE_D2_PT_3_68 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_2_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_2_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_2_IBUF,
      O => DO_2_OBUFE_D2_PT_3
    );
  DO_2_OBUFE_D2_69 : X_OR4
    port map (
      I0 => DO_2_OBUFE_D2_PT_0,
      I1 => DO_2_OBUFE_D2_PT_1,
      I2 => DO_2_OBUFE_D2_PT_2,
      I3 => DO_2_OBUFE_D2_PT_3,
      O => DO_2_OBUFE_D2
    );
  DO_2_OBUFE_TRST_70 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_2_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_2_OBUFE_TRST_IN1,
      O => DO_2_OBUFE_TRST
    );
  DO_3_OBUFE_71 : X_BUF
    port map (
      I => DO_3_OBUFE_Q,
      O => DO_3_OBUFE
    );
  DO_3_OBUFE_OE_72 : X_BUF
    port map (
      I => DO_3_OBUFE_BUFOE_OUT,
      O => DO_3_OBUFE_OE
    );
  DO_3_OBUFE_BUFOE_OUT_73 : X_BUF
    port map (
      I => DO_3_OBUFE_TRST,
      O => DO_3_OBUFE_BUFOE_OUT
    );
  DO_3_OBUFE_Q_74 : X_BUF
    port map (
      I => DO_3_OBUFE_D,
      O => DO_3_OBUFE_Q
    );
  DO_3_OBUFE_D_75 : X_XOR2
    port map (
      I0 => DO_3_OBUFE_D1,
      I1 => DO_3_OBUFE_D2,
      O => DO_3_OBUFE_D
    );
  DO_3_OBUFE_D1_76 : X_ZERO
    port map (
      O => DO_3_OBUFE_D1
    );
  DO_3_OBUFE_D2_PT_0_77 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_3_IBUF,
      O => DO_3_OBUFE_D2_PT_0
    );
  DO_3_OBUFE_D2_PT_1_78 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_3_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_3_IBUF,
      O => DO_3_OBUFE_D2_PT_1
    );
  DO_3_OBUFE_D2_PT_2_79 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_3_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_3_IBUF,
      O => DO_3_OBUFE_D2_PT_2
    );
  DO_3_OBUFE_D2_PT_3_80 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_3_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_3_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_3_IBUF,
      O => DO_3_OBUFE_D2_PT_3
    );
  DO_3_OBUFE_D2_81 : X_OR4
    port map (
      I0 => DO_3_OBUFE_D2_PT_0,
      I1 => DO_3_OBUFE_D2_PT_1,
      I2 => DO_3_OBUFE_D2_PT_2,
      I3 => DO_3_OBUFE_D2_PT_3,
      O => DO_3_OBUFE_D2
    );
  DO_3_OBUFE_TRST_82 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_3_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_3_OBUFE_TRST_IN1,
      O => DO_3_OBUFE_TRST
    );
  DO_4_OBUFE_83 : X_BUF
    port map (
      I => DO_4_OBUFE_Q,
      O => DO_4_OBUFE
    );
  DO_4_OBUFE_OE_84 : X_BUF
    port map (
      I => DO_4_OBUFE_BUFOE_OUT,
      O => DO_4_OBUFE_OE
    );
  DO_4_OBUFE_BUFOE_OUT_85 : X_BUF
    port map (
      I => DO_4_OBUFE_TRST,
      O => DO_4_OBUFE_BUFOE_OUT
    );
  DO_4_OBUFE_Q_86 : X_BUF
    port map (
      I => DO_4_OBUFE_D,
      O => DO_4_OBUFE_Q
    );
  DO_4_OBUFE_D_87 : X_XOR2
    port map (
      I0 => DO_4_OBUFE_D1,
      I1 => DO_4_OBUFE_D2,
      O => DO_4_OBUFE_D
    );
  DO_4_OBUFE_D1_88 : X_ZERO
    port map (
      O => DO_4_OBUFE_D1
    );
  DO_4_OBUFE_D2_PT_0_89 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_4_IBUF,
      O => DO_4_OBUFE_D2_PT_0
    );
  DO_4_OBUFE_D2_PT_1_90 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_4_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_4_IBUF,
      O => DO_4_OBUFE_D2_PT_1
    );
  DO_4_OBUFE_D2_PT_2_91 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_4_OBUFE_D2_PT_2_IN0,
      I1 => A0_IBUF,
      I2 => MR_2_4_IBUF,
      O => DO_4_OBUFE_D2_PT_2
    );
  DO_4_OBUFE_D2_PT_3_92 : X_AND3
    port map (
      I0 => NlwInverterSignal_DO_4_OBUFE_D2_PT_3_IN0,
      I1 => NlwInverterSignal_DO_4_OBUFE_D2_PT_3_IN1,
      I2 => MR_3_4_IBUF,
      O => DO_4_OBUFE_D2_PT_3
    );
  DO_4_OBUFE_D2_93 : X_OR4
    port map (
      I0 => DO_4_OBUFE_D2_PT_0,
      I1 => DO_4_OBUFE_D2_PT_1,
      I2 => DO_4_OBUFE_D2_PT_2,
      I3 => DO_4_OBUFE_D2_PT_3,
      O => DO_4_OBUFE_D2
    );
  DO_4_OBUFE_TRST_94 : X_AND2
    port map (
      I0 => NlwInverterSignal_DO_4_OBUFE_TRST_IN0,
      I1 => NlwInverterSignal_DO_4_OBUFE_TRST_IN1,
      O => DO_4_OBUFE_TRST
    );
  DO_5_OBUFE_95 : X_BUF
    port map (
      I => DO_5_OBUFE_Q,
      O => DO_5_OBUFE
    );
  DO_5_OBUFE_OE_96 : X_BUF
    port map (
      I => DO_5_OBUFE_BUFOE_OUT,
      O => DO_5_OBUFE_OE
    );
  DO_5_OBUFE_BUFOE_OUT_97 : X_BUF
    port map (
      I => DO_5_OBUFE_TRST,
      O => DO_5_OBUFE_BUFOE_OUT
    );
  DO_5_OBUFE_Q_98 : X_BUF
    port map (
      I => DO_5_OBUFE_D,
      O => DO_5_OBUFE_Q
    );
  DO_5_OBUFE_D_99 : X_XOR2
    port map (
      I0 => DO_5_OBUFE_D1,
      I1 => DO_5_OBUFE_D2,
      O => DO_5_OBUFE_D
    );
  DO_5_OBUFE_D1_100 : X_ZERO
    port map (
      O => DO_5_OBUFE_D1
    );
  DO_5_OBUFE_D2_PT_0_101 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => A0_IBUF,
      I2 => MR_0_5_IBUF,
      O => DO_5_OBUFE_D2_PT_0
    );
  DO_5_OBUFE_D2_PT_1_102 : X_AND3
    port map (
      I0 => A1_IBUF,
      I1 => NlwInverterSignal_DO_5_OBUFE_D2_PT_1_IN1,
      I2 => MR_1_5_IBUF,