sel4_1_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim sel4_1.nga sel4_1_timesim.vhd 
-- Input file    : sel4_1.nga
-- Output file   : sel4_1_timesim.vhd
-- Design name   : sel4_1.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC9572-10-TQ100 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity sel4_1 is
  port (
    CS : in STD_LOGIC := 'X'; 
    A1 : in STD_LOGIC := 'X'; 
    A0 : in STD_LOGIC := 'X'; 
    MR_3 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    MR_1 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    MR_0 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    MR_2 : in STD_LOGIC_VECTOR ( 7 downto 0 ); 
    DO : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end sel4_1;

architecture Structure of sel4_1 is
  signal CS_IBUF : STD_LOGIC; 
  signal A1_IBUF : STD_LOGIC; 
  signal A0_IBUF : STD_LOGIC; 
  signal MR_3_0_IBUF : STD_LOGIC; 
  signal MR_1_0_IBUF : STD_LOGIC; 
  signal MR_0_0_IBUF : STD_LOGIC; 
  signal MR_2_0_IBUF : STD_LOGIC; 
  signal MR_0_1_IBUF : STD_LOGIC; 
  signal MR_2_1_IBUF : STD_LOGIC; 
  signal MR_1_1_IBUF : STD_LOGIC; 
  signal MR_3_1_IBUF : STD_LOGIC; 
  signal MR_2_2_IBUF : STD_LOGIC; 
  signal MR_0_2_IBUF : STD_LOGIC; 
  signal MR_1_2_IBUF : STD_LOGIC; 
  signal MR_3_2_IBUF : STD_LOGIC; 
  signal MR_1_3_IBUF : STD_LOGIC; 
  signal MR_3_3_IBUF : STD_LOGIC; 
  signal MR_0_3_IBUF : STD_LOGIC; 
  signal MR_2_3_IBUF : STD_LOGIC; 
  signal MR_1_4_IBUF : STD_LOGIC; 
  signal MR_3_4_IBUF : STD_LOGIC; 
  signal MR_0_4_IBUF : STD_LOGIC; 
  signal MR_2_4_IBUF : STD_LOGIC; 
  signal MR_3_5_IBUF : STD_LOGIC; 
  signal MR_1_5_IBUF : STD_LOGIC; 
  signal MR_0_5_IBUF : STD_LOGIC; 
  signal MR_2_5_IBUF : STD_LOGIC; 
  signal MR_1_6_IBUF : STD_LOGIC; 
  signal MR_3_6_IBUF : STD_LOGIC; 
  signal MR_0_6_IBUF : STD_LOGIC; 
  signal MR_2_6_IBUF : STD_LOGIC; 
  signal MR_2_7_IBUF : STD_LOGIC; 
  signal MR_0_7_IBUF : STD_LOGIC; 
  signal MR_1_7_IBUF : STD_LOGIC; 
  signal MR_3_7_IBUF : STD_LOGIC; 
  signal DO_0_OBUFE : STD_LOGIC; 
  signal DO_0_OBUFE_OE : STD_LOGIC; 
  signal DO_1_OBUFE : STD_LOGIC; 
  signal DO_1_OBUFE_OE : STD_LOGIC; 
  signal DO_2_OBUFE : STD_LOGIC; 
  signal DO_2_OBUFE_OE : STD_LOGIC; 
  signal DO_3_OBUFE : STD_LOGIC; 
  signal DO_3_OBUFE_OE : STD_LOGIC; 
  signal DO_4_OBUFE : STD_LOGIC; 
  signal DO_4_OBUFE_OE : STD_LOGIC; 
  signal DO_5_OBUFE : STD_LOGIC; 
  signal DO_5_OBUFE_OE : STD_LOGIC; 
  signal DO_6_OBUFE : STD_LOGIC; 
  signal DO_6_OBUFE_OE : STD_LOGIC; 
  signal DO_7_OBUFE : STD_LOGIC; 
  signal DO_7_OBUFE_OE : STD_LOGIC; 
  signal DO_0_OBUFE_Q : STD_LOGIC; 
  signal DO_0_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_0_OBUFE_TRST : STD_LOGIC; 
  signal DO_0_OBUFE_D : STD_LOGIC; 
  signal DO_0_OBUFE_D1 : STD_LOGIC; 
  signal DO_0_OBUFE_D2 : STD_LOGIC; 
  signal DO_0_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_0_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_0_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_0_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_1_OBUFE_Q : STD_LOGIC; 
  signal DO_1_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_1_OBUFE_TRST : STD_LOGIC; 
  signal DO_1_OBUFE_D : STD_LOGIC; 
  signal DO_1_OBUFE_D1 : STD_LOGIC; 
  signal DO_1_OBUFE_D2 : STD_LOGIC; 
  signal DO_1_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_1_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_1_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_1_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_2_OBUFE_Q : STD_LOGIC; 
  signal DO_2_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_2_OBUFE_TRST : STD_LOGIC; 
  signal DO_2_OBUFE_D : STD_LOGIC; 
  signal DO_2_OBUFE_D1 : STD_LOGIC; 
  signal DO_2_OBUFE_D2 : STD_LOGIC; 
  signal DO_2_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_2_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_2_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_2_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_3_OBUFE_Q : STD_LOGIC; 
  signal DO_3_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_3_OBUFE_TRST : STD_LOGIC; 
  signal DO_3_OBUFE_D : STD_LOGIC; 
  signal DO_3_OBUFE_D1 : STD_LOGIC; 
  signal DO_3_OBUFE_D2 : STD_LOGIC; 
  signal DO_3_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_3_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_3_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_3_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_4_OBUFE_Q : STD_LOGIC; 
  signal DO_4_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_4_OBUFE_TRST : STD_LOGIC; 
  signal DO_4_OBUFE_D : STD_LOGIC; 
  signal DO_4_OBUFE_D1 : STD_LOGIC; 
  signal DO_4_OBUFE_D2 : STD_LOGIC; 
  signal DO_4_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_4_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_4_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_4_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_5_OBUFE_Q : STD_LOGIC; 
  signal DO_5_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_5_OBUFE_TRST : STD_LOGIC; 
  signal DO_5_OBUFE_D : STD_LOGIC; 
  signal DO_5_OBUFE_D1 : STD_LOGIC; 
  signal DO_5_OBUFE_D2 : STD_LOGIC; 
  signal DO_5_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_5_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_5_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_5_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_6_OBUFE_Q : STD_LOGIC; 
  signal DO_6_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_6_OBUFE_TRST : STD_LOGIC; 
  signal DO_6_OBUFE_D : STD_LOGIC; 
  signal DO_6_OBUFE_D1 : STD_LOGIC; 
  signal DO_6_OBUFE_D2 : STD_LOGIC; 
  signal DO_6_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_6_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_6_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_6_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal DO_7_OBUFE_Q : STD_LOGIC; 
  signal DO_7_OBUFE_BUFOE_OUT : STD_LOGIC; 
  signal DO_7_OBUFE_TRST : STD_LOGIC; 
  signal DO_7_OBUFE_D : STD_LOGIC; 
  signal DO_7_OBUFE_D1 : STD_LOGIC; 
  signal DO_7_OBUFE_D2 : STD_LOGIC; 
  signal DO_7_OBUFE_D2_PT_0 : STD_LOGIC; 
  signal DO_7_OBUFE_D2_PT_1 : STD_LOGIC; 
  signal DO_7_OBUFE_D2_PT_2 : STD_LOGIC; 
  signal DO_7_OBUFE_D2_PT_3 : STD_LOGIC; 
  signal NlwInverterSignal_DO_0_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_0_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_0_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_0_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_0_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_0_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_1_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_1_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_1_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_1_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_1_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_1_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_2_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_2_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_2_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_2_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_2_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_2_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_3_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_3_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_3_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_3_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_3_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_3_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_4_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_4_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_4_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_4_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_4_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_4_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_5_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_5_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_5_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_5_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_5_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_5_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_6_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_6_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_6_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_6_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_6_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_6_OBUFE_TRST_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_7_OBUFE_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_7_OBUFE_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_7_OBUFE_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_7_OBUFE_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DO_7_OBUFE_TRST_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DO_7_OBUFE_TRST_IN1 : STD_LOGIC; 
begin
  CS_IBUF_0 : X_BUF
    port map (
      I => CS,
      O => CS_IBUF
    );
  A1_IBUF_1 : X_BUF
    port map (
      I => A1,
      O => A1_IBUF
    );
  A0_IBUF_2 : X_BUF
    port map (
      I => A0,
      O => A0_IBUF
    );
  MR_3_0_IBUF_3 : X_BUF
    port map (
      I => MR_3(0),
      O => MR_3_0_IBUF
    );
  MR_1_0_IBUF_4 : X_BUF
    port map (
      I => MR_1(0),
      O => MR_1_0_IBUF
    );
  MR_0_0_IBUF_5 : X_BUF
    port map (
      I => MR_0(0),
      O => MR_0_0_IBUF
    );
  MR_2_0_IBUF_6 : X_BUF
    port map (
      I => MR_2(0),
      O => MR_2_0_IBUF
    );
  MR_0_1_IBUF_7 : X_BUF
    port map (
      I => MR_0(1),
      O => MR_0_1_IBUF
    );
  MR_2_1_IBUF_8 : X_BUF
    port map (
      I => MR_2(1),
      O => MR_2_1_IBUF
    );
  MR_1_1_IBUF_9 : X_BUF
    port map (
      I => MR_1(1),
      O => MR_1_1_IBUF
    );
  MR_3_1_IBUF_10 : X_BUF
    port map (
      I => MR_3(1),
      O => MR_3_1_IBUF
    );
  MR_2_2_IBUF_11 : X_BUF
    port map (
      I => MR_2(2),
      O => MR_2_2_IBUF
    );
  MR_0_2_IBUF_12 : X_BUF
    port map (
      I => MR_0(2),
      O => MR_0_2_IBUF
    );
  MR_1_2_IBUF_13 : X_BUF
    port map (
      I => MR_1(2),
      O => MR_1_2_IBUF
    );
  MR_3_2_IBUF_14 : X_BUF
    port map (
      I => MR_3(2),
      O => MR_3_2_IBUF
    );
  MR_1_3_IBUF_15 : X_BUF
    port map (
      I => MR_1(3),
      O => MR_1_3_IBUF
    );
  MR_3_3_IBUF_16 : X_BUF
    port map (
      I => MR_3(3),
      O => MR_3_3_IBUF
    );
  MR_0_3_IBUF_17 : X_BUF
    port map (
      I => MR_0(3),
      O => MR_0_3_IBUF
    );
  MR_2_3_IBUF_18 : X_BUF
    port map (
      I => MR_2(3),
      O => MR_2_3_IBUF
    );
  MR_1_4_IBUF_19 : X_BUF
    port map (
      I => MR_1(4),
      O => MR_1_4_IBUF
    );
  MR_3_4_IBUF_20 : X_BUF
    port map (
      I => MR_3(4),
      O => MR_3_4_IBUF
    );
  MR_0_4_IBUF_21 : X_BUF
    port map (
      I => MR_0(4),
      O => MR_0_4_IBUF
    );
  MR_2_4_IBUF_22 : X_BUF
    port map (
      I => MR_2(4),
      O => MR_2_4_IBUF
    );
  MR_3_5_IBUF_23 : X_BUF
    port map (
      I => MR_3(5),
      O => MR_3_5_IBUF
    );
  MR_1_5_IBUF_24 : X_BUF
    port map (
      I => MR_1(5),
      O => MR_1_5_IBUF
    );
  MR_0_5_IBUF_25 : X_BUF
    port map (
      I => MR_0(5),
      O => MR_0_5_IBUF
    );
  MR_2_5_IBUF_26 : X_BUF
    port map (
      I => MR_2(5),
      O => MR_2_5_IBUF
    );
  MR_1_6_IBUF_27 : X_BUF
    port map (
      I => MR_1(6),
      O => MR_1_6_IBUF
    );
  MR_3_6_IBUF_28 : X_BUF
    port map (
      I => MR_3(6),
      O => MR_3_6_IBUF
    );
  MR_0_6_IBUF_29 : X_BUF
    port map (
      I => MR_0(6),
      O => MR_0_6_IBUF
    );
  MR_2_6_IBUF_30 : X_BUF
    port map (
      I => MR_2(6),
      O => MR_2_6_IBUF
    );
  MR_2_7_IBUF_31 : X_BUF
    port map (
      I => MR_2(7),
      O => MR_2_7_IBUF
    );
  MR_0_7_IBUF_32 : X_BUF
    port map (
      I => MR_0(7),
      O => MR_0_7_IBUF
    );
  MR_1_7_IBUF_33 : X_BUF
    port map (
      I => MR_1(7),
      O => MR_1_7_IBUF
    );
  MR_3_7_IBUF_34 : X_BUF
    port map (
      I => MR_3(7),
      O => MR_3_7_IBUF
    );
  DO_0_Q : X_TRI
    port map (
      I => DO_0_OBUFE,
      CTL => DO_0_OBUFE_OE,
      O => DO(0)
    );
  DO_1_Q : X_TRI
    port map (
      I => DO_1_OBUFE,
      CTL => DO_1_OBUFE_OE,
      O => DO(1)
    );
  DO_2_Q : X_TRI
    port map (
      I => DO_2_OBUFE,
      CTL => DO_2_OBUFE_OE,
      O => DO(2)
    );
  DO_3_Q : X_TRI
    port map (
      I => DO_3_OBUFE,
      CTL => DO_3_OBUFE_OE,
      O => DO(3)
    );
  DO_4_Q : X_TRI
    port map (
      I => DO_4_OBUFE,
      CTL => DO_4_OBUFE_OE,
      O => DO(4)
    );