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Release 6.3i - CPLD HTML Report Processor G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.




Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.3i - sch2vhdl G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:13 - Net "CS3" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC2" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC4" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC3" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC1" is connected to source pins and/or IO ports
   while there is no load pin connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/FPGA/TEST/xc_9572/count9.vhd in Library work.
Architecture behavioral of Entity count9 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/d5_32e.vhd in Library work.
Architecture behavioral of Entity d5_32e is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/dq24.vhd in Library work.
Architecture behavioral of Entity dq24 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/dq024.vhd in Library work.
Architecture behavioral of Entity dq024 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/logic.vhd in Library work.
Architecture behavioral of Entity logic is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/mdecode.vhd in Library work.
Architecture behavioral of Entity mdecode is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/sel4_1.vhd in Library work.
Architecture behavioral of Entity sel4_1 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/DECODE.vhd in Library work.
Architecture behavioral of Entity decode is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/top.vhf in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <dq024> (Architecture <behavioral>).
Entity <dq024> analyzed. Unit <dq024> generated.

Analyzing Entity <d5_32e> (Architecture <behavioral>).
Entity <d5_32e> analyzed. Unit <d5_32e> generated.

Analyzing Entity <dq24> (Architecture <behavioral>).
Entity <dq24> analyzed. Unit <dq24> generated.

Analyzing Entity <logic> (Architecture <behavioral>).
Entity <logic> analyzed. Unit <logic> generated.

Analyzing Entity <mdecode> (Architecture <behavioral>).
Entity <mdecode> analyzed. Unit <mdecode> generated.

Analyzing Entity <count9> (Architecture <behavioral>).
Entity <count9> analyzed. Unit <count9> generated.

Analyzing Entity <sel4_1> (Architecture <behavioral>).
INFO:Xst:1561 - D:/FPGA/TEST/xc_9572/sel4_1.vhd line 51: Mux is complete : default of case is discarded
Entity <sel4_1> analyzed. Unit <sel4_1> generated.

Analyzing Entity <decode> (Architecture <behavioral>).
Entity <decode> analyzed. Unit <decode> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count9>.
    Related source file is D:/FPGA/TEST/xc_9572/count9.vhd.
    Found 8-bit updown counter for signal <Temp>.
    Summary:
	inferred   1 Counter(s).
Unit <count9> synthesized.


Synthesizing Unit <dq24>.
    Related source file is D:/FPGA/TEST/xc_9572/dq24.vhd.
Unit <dq24> synthesized.


Synthesizing Unit <d5_32e>.
    Related source file is D:/FPGA/TEST/xc_9572/d5_32e.vhd.
Unit <d5_32e> synthesized.


Synthesizing Unit <decode>.
    Related source file is D:/FPGA/TEST/xc_9572/DECODE.vhd.
Unit <decode> synthesized.


Synthesizing Unit <sel4_1>.
    Related source file is D:/FPGA/TEST/xc_9572/sel4_1.vhd.
    Found 8-bit tristate buffer for signal <DO>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0001> created at line 47.
    Summary:
	inferred   8 Tristate(s).
Unit <sel4_1> synthesized.


Synthesizing Unit <mdecode>.
    Related source file is D:/FPGA/TEST/xc_9572/mdecode.vhd.
    Found 2-bit register for signal <temp0<3:2>>.
    Found 2-bit register for signal <temp1<3:2>>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <mdecode> synthesized.


Synthesizing Unit <logic>.
    Related source file is D:/FPGA/TEST/xc_9572/logic.vhd.
Unit <logic> synthesized.


Synthesizing Unit <dq024>.
    Related source file is D:/FPGA/TEST/xc_9572/dq024.vhd.
WARNING:Xst:647 - Input <D<6:5>> is never used.
Unit <dq024> synthesized.


Synthesizing Unit <top>.
    Related source file is D:/FPGA/TEST/xc_9572/top.vhf.
WARNING:Xst:646 - Signal <NC1> is assigned but never used.
WARNING:Xst:646 - Signal <CS3> is assigned but never used.
WARNING:Xst:646 - Signal <NC2> is assigned but never used.
WARNING:Xst:646 - Signal <NC3> is assigned but never used.
WARNING:Xst:646 - Signal <NC4> is assigned but never used.
Unit <top> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
 8-bit updown counter              : 2
# Registers                        : 4
 1-bit register                    : 4
# Multiplexers                     : 1
 8-bit 4-to-1 multiplexer          : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1348 - Unit sel4_1 is merged (output interface has tristates)
WARNING:Xst:1355 - Unit logic is merged (low complexity)

Optimizing unit <top> ...

Optimizing unit <decode> ...

Optimizing unit <d5_32e> ...

Optimizing unit <dq24> ...

Optimizing unit <dq024> ...

Optimizing unit <count9> ...

Optimizing unit <mdecode> ...
Completed process "Synthesize".



Started process "Translate".

Release 6.3i - ngdbuild G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc top.ucf -p xc9500 top.ngc top.ngd 

Reading NGO file "D:/FPGA/TEST/xc_9572/top.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "top.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41368 kilobytes

Writing NGD file "top.ngd" ...

Writing NGDBUILD log file "top.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Fit".

Release 6.3i - CPLD Optimizer/Partitioner G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Considering device XC9572-10-TQ100.
Flattening design..
Timing optimization.......
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 53 equations into 4 function blocks......WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<7> to allow all signals assigned to this function
   block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<6> to allow all signals assigned to this function
   block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<5> to allow all signals assigned to this function
   block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<4> to allow all signals assigned to this function
   block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<3> to allow all signals assigned to this function
   block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<2> to allow all signals assigned to this function
   block to be placed.
WARNING:Cpld:897 - Unable to map all desired signals into function block, FB1.
   Buffering output signal D<1> to allow all signals assigned to this function
   block to be placed.
............................................ERROR:Cpld:892 - Cannot place signal XLXI_57/QQ8<7>. Consider reducing the
   collapsing input limit or the product term limit to prevent the fitter from
   creating high input and/or high product term functions.
See the fitter report for details.
..........

ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
   the selected implementation options.
ERROR: Fit failed
Reason: 
Process "Fit" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.3i - sch2vhdl G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
WARNING:DesignEntry:13 - Net "CS3" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC2" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC4" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC3" is connected to source pins and/or IO ports
   while there is no load pin connected to it
WARNING:DesignEntry:13 - Net "NC1" is connected to source pins and/or IO ports
   while there is no load pin connected to it
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/FPGA/TEST/xc_9572/count9.vhd in Library work.
Architecture behavioral of Entity count9 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/d5_32e.vhd in Library work.
Architecture behavioral of Entity d5_32e is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/dq24.vhd in Library work.
Architecture behavioral of Entity dq24 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/dq024.vhd in Library work.
Architecture behavioral of Entity dq024 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/logic.vhd in Library work.
Architecture behavioral of Entity logic is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/mdecode.vhd in Library work.
Architecture behavioral of Entity mdecode is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/sel4_1.vhd in Library work.
Architecture behavioral of Entity sel4_1 is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/DECODE.vhd in Library work.
Architecture behavioral of Entity decode is up to date.
Compiling vhdl file D:/FPGA/TEST/xc_9572/top.vhf in Library work.
Entity <top> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top> (Architecture <behavioral>).
Entity <top> analyzed. Unit <top> generated.

Analyzing Entity <dq024> (Architecture <behavioral>).
Entity <dq024> analyzed. Unit <dq024> generated.

Analyzing Entity <d5_32e> (Architecture <behavioral>).
Entity <d5_32e> analyzed. Unit <d5_32e> generated.

Analyzing Entity <dq24> (Architecture <behavioral>).
Entity <dq24> analyzed. Unit <dq24> generated.

Analyzing Entity <logic> (Architecture <behavioral>).
Entity <logic> analyzed. Unit <logic> generated.

Analyzing Entity <mdecode> (Architecture <behavioral>).
Entity <mdecode> analyzed. Unit <mdecode> generated.

Analyzing Entity <count9> (Architecture <behavioral>).
Entity <count9> analyzed. Unit <count9> generated.

Analyzing Entity <sel4_1> (Architecture <behavioral>).
INFO:Xst:1561 - D:/FPGA/TEST/xc_9572/sel4_1.vhd line 51: Mux is complete : default of case is discarded
Entity <sel4_1> analyzed. Unit <sel4_1> generated.

Analyzing Entity <decode> (Architecture <behavioral>).
Entity <decode> analyzed. Unit <decode> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <count9>.
    Related source file is D:/FPGA/TEST/xc_9572/count9.vhd.
    Found 8-bit updown counter for signal <Temp>.
    Summary:
	inferred   1 Counter(s).
Unit <count9> synthesized.


Synthesizing Unit <dq24>.
    Related source file is D:/FPGA/TEST/xc_9572/dq24.vhd.
Unit <dq24> synthesized.


Sy