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=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 2 8-bit updown counter : 2# Registers : 4 1-bit register : 4# Multiplexers : 1 2-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <mdecode> ...Optimizing unit <count9> ...Completed process "Synthesize".
Started process "Translate".Release 6.3i - ngdbuild G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc mdecode.ucf -p xc9500 mdecode.ngcmdecode.ngd Reading NGO file "D:/FPGA/TEST/xc_9572/mdecode.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "mdecode.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 39320 kilobytesWriting NGD file "mdecode.ngd" ...Writing NGDBUILD log file "mdecode.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3i - CPLD Optimizer/Partitioner G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:1007 - Removing unused input(s) 'RD'. The input(s) are unused after optimization. Please verify functionality via simulation.Considering device XC9572-10-TQ100.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 28 equations into 4 function blocks............Design mdecode has been optimized and fit into device XC9572-10-TQ100.Completed process "Fit".
Started process "Generate Programming File".Release 6.3i - Programming File Generator G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate HTML report".Release 6.3i - CPLD HTML Report Processor G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/FPGA/TEST/xc_9572/count9.vhd in Library work.Architecture behavioral of Entity count9 is up to date.Compiling vhdl file D:/FPGA/TEST/xc_9572/mdecode.vhd in Library work.Entity <mdecode> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <mdecode> (Architecture <behavioral>).Entity <mdecode> analyzed. Unit <mdecode> generated.Analyzing Entity <count9> (Architecture <behavioral>).Entity <count9> analyzed. Unit <count9> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <count9>. Related source file is D:/FPGA/TEST/xc_9572/count9.vhd. Found 8-bit updown counter for signal <Temp>. Summary: inferred 1 Counter(s).Unit <count9> synthesized.Synthesizing Unit <mdecode>. Related source file is D:/FPGA/TEST/xc_9572/mdecode.vhd.WARNING:Xst:647 - Input <CS_MC> is never used. Found 2-bit register for signal <temp0<3:2>>. Found 2-bit register for signal <temp1<3:2>>. Found 8 1-bit 2-to-1 multiplexers. Summary: inferred 2 D-type flip-flop(s).Unit <mdecode> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 2 8-bit updown counter : 2# Registers : 4 1-bit register : 4# Multiplexers : 1 2-to-1 multiplexer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <mdecode> ...Optimizing unit <count9> ...Completed process "Synthesize".
Started process "Translate".Release 6.3i - ngdbuild G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc mdecode.ucf -p xc9500 mdecode.ngcmdecode.ngd Reading NGO file "D:/FPGA/TEST/xc_9572/mdecode.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "mdecode.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 39320 kilobytesWriting NGD file "mdecode.ngd" ...Writing NGDBUILD log file "mdecode.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3i - CPLD Optimizer/Partitioner G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.WARNING:Cpld:1007 - Removing unused input(s) 'CS_MC'. The input(s) are unused after optimization. Please verify functionality via simulation.Considering device XC9572-10-TQ100.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 28 equations into 4 function blocks............Design mdecode has been optimized and fit into device XC9572-10-TQ100.Completed process "Fit".
Started process "Generate Programming File".Release 6.3i - Programming File Generator G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate HTML report".Release 6.3i - CPLD HTML Report Processor G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file D:/FPGA/TEST/xc_9572/count9.vhd in Library work.Architecture behavioral of Entity count9 is up to date.Compiling vhdl file D:/FPGA/TEST/xc_9572/mdecode.vhd in Library work.Entity <mdecode> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <mdecode> (Architecture <behavioral>).Entity <mdecode> analyzed. Unit <mdecode> generated.Analyzing Entity <count9> (Architecture <behavioral>).Entity <count9> analyzed. Unit <count9> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <count9>. Related source file is D:/FPGA/TEST/xc_9572/count9.vhd. Found 8-bit updown counter for signal <Temp>. Summary: inferred 1 Counter(s).Unit <count9> synthesized.Synthesizing Unit <mdecode>. Related source file is D:/FPGA/TEST/xc_9572/mdecode.vhd. Found 2-bit register for signal <temp0<3:2>>. Found 2-bit register for signal <temp1<3:2>>. Summary: inferred 2 D-type flip-flop(s).Unit <mdecode> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 2 8-bit updown counter : 2# Registers : 4 1-bit register : 4==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <mdecode> ...Optimizing unit <count9> ...Completed process "Synthesize".
Started process "Translate".Release 6.3i - ngdbuild G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc mdecode.ucf -p xc9500 mdecode.ngcmdecode.ngd Reading NGO file "D:/FPGA/TEST/xc_9572/mdecode.ngc" ...Reading component libraries for design expansion...Annotating constraints to design from file "mdecode.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 39320 kilobytesWriting NGD file "mdecode.ngd" ...Writing NGDBUILD log file "mdecode.bld"...NGDBUILD done.Completed process "Translate".
Started process "Fit".Release 6.3i - CPLD Optimizer/Partitioner G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Considering device XC9572-10-TQ100.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 28 equations into 4 function blocks............Design mdecode has been optimized and fit into device XC9572-10-TQ100.Completed process "Fit".
Started process "Generate Programming File".Release 6.3i - Programming File Generator G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Generate Programming File".
Started process "Generate HTML report".⌨️ 快捷键说明
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