d3_8l.syr

xilinx xc9572 cpld 实现的伺服电机控制器

Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: d3_8l.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : d3_8l.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : d3_8l
Output Format                      : NGC
Target Device                      : xc9500

---- Source Options
Top Module Name                    : d3_8l
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : ONLY
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : d3_8l.lso
verilog2001                        : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/FPGA/TEST/xc9572/d3_8l.vhd in Library work.
Architecture behavioral of Entity d3_8l is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <d3_8l> (Architecture <behavioral>).
INFO:Xst:1561 - D:/FPGA/TEST/xc9572/d3_8l.vhd line 61: Mux is complete : default of case is discarded
Entity <d3_8l> analyzed. Unit <d3_8l> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <d3_8l>.
    Related source file is D:/FPGA/TEST/xc9572/d3_8l.vhd.
Unit <d3_8l> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : d3_8l.ngr
Keep Hierarchy                     : YES
Target Technology                  : xc9500
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 12

Cell Usage :
=========================================================================
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