📄 dq024.rpt
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FTCPE_DQ20: FTCPE port map (DQ20,DQ20_T,WR,REST,'0');
DQ20_T <= ((NOT G AND NOT D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ20_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ20_OBUF.FBK.LFBK));
FTCPE_DQ21: FTCPE port map (DQ21,DQ21_T,WR,REST,'0');
DQ21_T <= ((NOT G AND NOT D(1) AND D(0) AND D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ21_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND D(0) AND D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ21_OBUF.FBK.LFBK));
FTCPE_DQ22: FTCPE port map (DQ22,DQ22_T,WR,REST,'0');
DQ22_T <= ((NOT G AND D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ22_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ22_OBUF.FBK.LFBK));
FTCPE_DQ23: FTCPE port map (DQ23,DQ23_T,WR,REST,'0');
DQ23_T <= ((NOT G AND D(1) AND D(0) AND D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ23_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND D(0) AND D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ23_OBUF.FBK.LFBK));
FTCPE_DQ2: FTCPE port map (DQ2,DQ2_T,WR,REST,'0');
DQ2_T <= ((NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ2_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ2_OBUF.FBK.LFBK));
FTCPE_DQ3: FTCPE port map (DQ3,DQ3_T,WR,REST,'0');
DQ3_T <= ((NOT G AND D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ3_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ3_OBUF.FBK.LFBK));
FTCPE_DQ4: FTCPE port map (DQ4,DQ4_T,WR,REST,'0');
DQ4_T <= ((NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ4_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ4_OBUF.FBK.LFBK));
FTCPE_DQ5: FTCPE port map (DQ5,DQ5_T,WR,REST,'0');
DQ5_T <= ((NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ5_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ5_OBUF.FBK.LFBK));
FTCPE_DQ6: FTCPE port map (DQ6,DQ6_T,WR,REST,'0');
DQ6_T <= ((NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ6_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ6_OBUF.FBK.LFBK));
FTCPE_DQ7: FTCPE port map (DQ7,DQ7_T,WR,REST,'0');
DQ7_T <= ((NOT G AND D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND D(7) AND
NOT DQ7_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND D(2) AND NOT D(7) AND
DQ7_OBUF.FBK.LFBK));
FTCPE_DQ8: FTCPE port map (DQ8,DQ8_T,WR,REST,'0');
DQ8_T <= ((NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND D(7) AND
NOT DQ8_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND NOT D(7) AND
DQ8_OBUF.FBK.LFBK));
FTCPE_DQ9: FTCPE port map (DQ9,DQ9_T,WR,REST,'0');
DQ9_T <= ((NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND D(7) AND
NOT DQ9_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND NOT D(7) AND
DQ9_OBUF.FBK.LFBK));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC9572-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TIE 51 VCC
2 NC 52 REST
3 TIE 53 TIE
4 TIE 54 DQ13
5 VCC 55 TIE
6 DQ7 56 D<3>
7 NC 57 VCC
8 TIE 58 TIE
9 TIE 59 TIE
10 TIE 60 DQ15
11 DQ8 61 TIE
12 TIE 62 GND
13 TIE 63 DQ17
14 D<7> 64 G
15 DQ20 65 DQ18
16 TIE 66 DQ10
17 DQ23 67 TIE
18 DQ1 68 D<2>
19 NC 69 GND
20 TIE 70 TIE
21 GND 71 TIE
22 TIE 72 DQ12
23 TIE 73 NC
24 NC 74 D<0>
25 TIE 75 GND
26 VCC 76 TIE
27 TIE 77 DQ14
28 TIE 78 TIE
29 DQ22 79 TIE
30 TIE 80 NC
31 GND 81 DQ16
32 D<1> 82 TIE
33 DQ21 83 TDO
34 NC 84 GND
35 TIE 85 DQ2
36 TIE 86 DQ3
37 TIE 87 TIE
38 VCC 88 VCC
39 TIE 89 TIE
40 DQ19 90 WR
41 DQ0 91 DQ5
42 TIE 92 DQ4
43 NC 93 TIE
44 GND 94 TIE
45 TDI 95 D<4>
46 NC 96 DQ9
47 TMS 97 DQ6
48 TCK 98 VCC
49 TIE 99 TIE
50 DQ11 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : AUTO
Ground on Unused IOs : OFF
Global Clock Optimization : OFF
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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