📄 dq024.rpt
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Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
DQ0 4 0 0 1 FB3_1 STD 41 I/O O
(unused) 0 0 0 5 FB3_2 32 I/O I
(unused) 0 0 0 5 FB3_3 49 I/O
DQ11 4 0 0 1 FB3_4 STD 50 I/O O
(unused) 0 0 0 5 FB3_5 35 I/O
(unused) 0 0 0 5 FB3_6 53 I/O
DQ13 4 0 0 1 FB3_7 STD 54 I/O O
(unused) 0 0 0 5 FB3_8 37 I/O
(unused) 0 0 0 5 FB3_9 42 I/O
DQ15 4 0 0 1 FB3_10 STD 60 I/O O
(unused) 0 0 0 5 FB3_11 52 I/O I
(unused) 0 0 0 5 FB3_12 61 I/O
DQ17 4 0 0 1 FB3_13 STD 63 I/O O
(unused) 0 0 0 5 FB3_14 55 I/O
(unused) 0 0 0 5 FB3_15 56 I/O I
DQ18 4 0 0 1 FB3_16 STD 65 I/O O
(unused) 0 0 0 5 FB3_17 58 I/O
(unused) 0 0 0 5 FB3_18 59 I/O
Signals Used by Logic in Function Block
1: DQ0_OBUF.FBK.LFBK 6: DQ18_OBUF.FBK.LFBK
11: D<4>
2: DQ11_OBUF.FBK.LFBK
7: D<0> 12: D<7>
3: DQ13_OBUF.FBK.LFBK
8: D<1> 13: G
4: DQ15_OBUF.FBK.LFBK
9: D<2> 14: REST
5: DQ17_OBUF.FBK.LFBK
10: D<3> 15: WR
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ0 X.....XXXXXXXXX......................... 10 10
DQ11 .X....XXXXXXXXX......................... 10 10
DQ13 ..X...XXXXXXXXX......................... 10 10
DQ15 ...X..XXXXXXXXX......................... 10 10
DQ17 ....X.XXXXXXXXX......................... 10 10
DQ18 .....XXXXXXXXXX......................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
DQ10 4 0 0 1 FB4_1 STD 66 I/O O
(unused) 0 0 0 5 FB4_2 64 I/O I
(unused) 0 0 0 5 FB4_3 71 I/O
DQ12 4 0 0 1 FB4_4 STD 72 I/O O
(unused) 0 0 0 5 FB4_5 67 I/O
(unused) 0 0 0 5 FB4_6 76 I/O
DQ14 4 0 0 1 FB4_7 STD 77 I/O O
(unused) 0 0 0 5 FB4_8 68 I/O I
(unused) 0 0 0 5 FB4_9 70 I/O
DQ16 4 0 0 1 FB4_10 STD 81 I/O O
(unused) 0 0 0 5 FB4_11 74 I/O I
(unused) 0 0 0 5 FB4_12 82 I/O
DQ2 4 0 0 1 FB4_13 STD 85 I/O O
(unused) 0 0 0 5 FB4_14 78 I/O
(unused) 0 0 0 5 FB4_15 89 I/O
DQ3 4 0 0 1 FB4_16 STD 86 I/O O
(unused) 0 0 0 5 FB4_17 90 I/O I
(unused) 0 0 0 5 FB4_18 79 I/O
Signals Used by Logic in Function Block
1: DQ10_OBUF.FBK.LFBK
6: DQ3_OBUF.FBK.LFBK 11: D<4>
2: DQ12_OBUF.FBK.LFBK
7: D<0> 12: D<7>
3: DQ14_OBUF.FBK.LFBK
8: D<1> 13: G
4: DQ16_OBUF.FBK.LFBK
9: D<2> 14: REST
5: DQ2_OBUF.FBK.LFBK 10: D<3> 15: WR
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ10 X.....XXXXXXXXX......................... 10 10
DQ12 .X....XXXXXXXXX......................... 10 10
DQ14 ..X...XXXXXXXXX......................... 10 10
DQ16 ...X..XXXXXXXXX......................... 10 10
DQ2 ....X.XXXXXXXXX......................... 10 10
DQ3 .....XXXXXXXXXX......................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
FTCPE_DQ0: FTCPE port map (DQ0,DQ0_T,WR,REST,'0');
DQ0_T <= ((NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ0_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ0_OBUF.FBK.LFBK));
FTCPE_DQ10: FTCPE port map (DQ10,DQ10_T,WR,REST,'0');
DQ10_T <= ((NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND D(7) AND
NOT DQ10_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND NOT D(7) AND
DQ10_OBUF.FBK.LFBK));
FTCPE_DQ11: FTCPE port map (DQ11,DQ11_T,WR,REST,'0');
DQ11_T <= ((NOT G AND D(1) AND D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND D(7) AND
NOT DQ11_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND D(0) AND NOT D(4) AND D(3) AND NOT D(2) AND NOT D(7) AND
DQ11_OBUF.FBK.LFBK));
FTCPE_DQ12: FTCPE port map (DQ12,DQ12_T,WR,REST,'0');
DQ12_T <= ((NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND D(2) AND D(7) AND
NOT DQ12_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND D(2) AND NOT D(7) AND
DQ12_OBUF.FBK.LFBK));
FTCPE_DQ13: FTCPE port map (DQ13,DQ13_T,WR,REST,'0');
DQ13_T <= ((NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND D(3) AND D(2) AND D(7) AND
NOT DQ13_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND D(3) AND D(2) AND NOT D(7) AND
DQ13_OBUF.FBK.LFBK));
FTCPE_DQ14: FTCPE port map (DQ14,DQ14_T,WR,REST,'0');
DQ14_T <= ((NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND D(2) AND D(7) AND
NOT DQ14_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND NOT D(0) AND NOT D(4) AND D(3) AND D(2) AND NOT D(7) AND
DQ14_OBUF.FBK.LFBK));
FTCPE_DQ15: FTCPE port map (DQ15,DQ15_T,WR,REST,'0');
DQ15_T <= ((NOT G AND D(1) AND D(0) AND NOT D(4) AND D(3) AND D(2) AND D(7) AND
NOT DQ15_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND D(0) AND NOT D(4) AND D(3) AND D(2) AND NOT D(7) AND
DQ15_OBUF.FBK.LFBK));
FTCPE_DQ16: FTCPE port map (DQ16,DQ16_T,WR,REST,'0');
DQ16_T <= ((NOT G AND NOT D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ16_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ16_OBUF.FBK.LFBK));
FTCPE_DQ17: FTCPE port map (DQ17,DQ17_T,WR,REST,'0');
DQ17_T <= ((NOT G AND NOT D(1) AND D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ17_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ17_OBUF.FBK.LFBK));
FTCPE_DQ18: FTCPE port map (DQ18,DQ18_T,WR,REST,'0');
DQ18_T <= ((NOT G AND D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ18_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND NOT D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ18_OBUF.FBK.LFBK));
FTCPE_DQ19: FTCPE port map (DQ19,DQ19_T,WR,REST,'0');
DQ19_T <= ((NOT G AND D(1) AND D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ19_OBUF.FBK.LFBK)
OR (NOT G AND D(1) AND D(0) AND D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ19_OBUF.FBK.LFBK));
FTCPE_DQ1: FTCPE port map (DQ1,DQ1_T,WR,REST,'0');
DQ1_T <= ((NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND D(7) AND
NOT DQ1_OBUF.FBK.LFBK)
OR (NOT G AND NOT D(1) AND D(0) AND NOT D(4) AND NOT D(3) AND NOT D(2) AND NOT D(7) AND
DQ1_OBUF.FBK.LFBK));
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