📄 dq024.rpt
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cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: dq024 Date: 4-12-2006, 3:02PM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
24 /72 ( 33%) 96 /360 ( 27%) 24 /72 ( 33%) 33 /72 ( 46%) 60 /144 ( 42%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 9 9 | I/O : 33 33
Output : 24 24 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 33 33
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 24
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 24 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 24 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld:1007 - Removing unused input(s) 'D<5>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<6>'. The input(s) are unused
after optimization. Please verify functionality via simulation.
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
DQ0 4 10 FB3_1 STD SLOW 41 I/O O RESET
DQ1 4 10 FB1_3 STD SLOW 18 I/O O RESET
DQ10 4 10 FB4_1 STD SLOW 66 I/O O RESET
DQ11 4 10 FB3_4 STD SLOW 50 I/O O RESET
DQ12 4 10 FB4_4 STD SLOW 72 I/O O RESET
DQ13 4 10 FB3_7 STD SLOW 54 I/O O RESET
DQ14 4 10 FB4_7 STD SLOW 77 I/O O RESET
DQ15 4 10 FB3_10 STD SLOW 60 I/O O RESET
DQ16 4 10 FB4_10 STD SLOW 81 I/O O RESET
DQ17 4 10 FB3_13 STD SLOW 63 I/O O RESET
DQ18 4 10 FB3_16 STD SLOW 65 I/O O RESET
DQ19 4 10 FB1_18 STD SLOW 40 I/O O RESET
DQ2 4 10 FB4_13 STD SLOW 85 I/O O RESET
DQ20 4 10 FB1_6 STD SLOW 15 I/O O RESET
DQ21 4 10 FB1_12 STD SLOW 33 I/O O RESET
DQ22 4 10 FB1_15 STD SLOW 29 I/O O RESET
DQ23 4 10 FB1_8 STD SLOW 17 I/O O RESET
DQ3 4 10 FB4_16 STD SLOW 86 I/O O RESET
DQ4 4 10 FB2_18 STD SLOW 92 I/O O RESET
DQ5 4 10 FB2_3 STD SLOW 91 I/O O RESET
DQ6 4 10 FB2_8 STD SLOW 97 I/O O RESET
DQ7 4 10 FB2_12 STD SLOW 6 I/O O RESET
DQ8 4 10 FB2_15 STD SLOW 11 I/O O RESET
DQ9 4 10 FB2_6 STD SLOW 96 I/O O RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
D<0> FB4_11 74 I/O I
D<1> FB3_2 32 I/O I
D<2> FB4_8 68 I/O I
D<3> FB3_15 56 I/O I
D<4> FB2_5 95 I/O I
D<7> FB1_5 14 I/O I
G FB4_2 64 I/O I
REST FB3_11 52 I/O I
WR FB4_17 90 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 6 15 15 24 6/0 18
FB2 6 15 15 24 6/0 18
FB3 6 15 15 24 6/0 18
FB4 6 15 15 24 6/0 18
---- ----- ----- -----
24 96 24/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 16 I/O
(unused) 0 0 0 5 FB1_2 13 I/O
DQ1 4 0 0 1 FB1_3 STD 18 I/O O
(unused) 0 0 0 5 FB1_4 20 I/O
(unused) 0 0 0 5 FB1_5 14 I/O I
DQ20 4 0 0 1 FB1_6 STD 15 I/O O
(unused) 0 0 0 5 FB1_7 25 I/O
DQ23 4 0 0 1 FB1_8 STD 17 I/O O
(unused) 0 0 0 5 FB1_9 22 GCK/I/O
(unused) 0 0 0 5 FB1_10 28 I/O
(unused) 0 0 0 5 FB1_11 23 GCK/I/O
DQ21 4 0 0 1 FB1_12 STD 33 I/O O
(unused) 0 0 0 5 FB1_13 36 I/O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O
DQ22 4 0 0 1 FB1_15 STD 29 I/O O
(unused) 0 0 0 5 FB1_16 39 I/O
(unused) 0 0 0 5 FB1_17 30 I/O
DQ19 4 0 0 1 FB1_18 STD 40 I/O O
Signals Used by Logic in Function Block
1: DQ19_OBUF.FBK.LFBK
6: DQ23_OBUF.FBK.LFBK
11: D<4>
2: DQ1_OBUF.FBK.LFBK 7: D<0> 12: D<7>
3: DQ20_OBUF.FBK.LFBK
8: D<1> 13: G
4: DQ21_OBUF.FBK.LFBK
9: D<2> 14: REST
5: DQ22_OBUF.FBK.LFBK
10: D<3> 15: WR
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ1 .X....XXXXXXXXX......................... 10 10
DQ20 ..X...XXXXXXXXX......................... 10 10
DQ23 .....XXXXXXXXXX......................... 10 10
DQ21 ...X..XXXXXXXXX......................... 10 10
DQ22 ....X.XXXXXXXXX......................... 10 10
DQ19 X.....XXXXXXXXX......................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 15/21
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
(unused) 0 0 0 5 FB2_2 94 I/O
DQ5 4 0 0 1 FB2_3 STD 91 I/O O
(unused) 0 0 0 5 FB2_4 93 I/O
(unused) 0 0 0 5 FB2_5 95 I/O I
DQ9 4 0 0 1 FB2_6 STD 96 I/O O
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
DQ6 4 0 0 1 FB2_8 STD 97 I/O O
(unused) 0 0 0 5 FB2_9 99 GSR/I/O
(unused) 0 0 0 5 FB2_10 1 I/O
(unused) 0 0 0 5 FB2_11 4 GTS/I/O
DQ7 4 0 0 1 FB2_12 STD 6 I/O O
(unused) 0 0 0 5 FB2_13 8 I/O
(unused) 0 0 0 5 FB2_14 9 I/O
DQ8 4 0 0 1 FB2_15 STD 11 I/O O
(unused) 0 0 0 5 FB2_16 10 I/O
(unused) 0 0 0 5 FB2_17 12 I/O
DQ4 4 0 0 1 FB2_18 STD 92 I/O O
Signals Used by Logic in Function Block
1: DQ4_OBUF.FBK.LFBK 6: DQ9_OBUF.FBK.LFBK 11: D<4>
2: DQ5_OBUF.FBK.LFBK 7: D<0> 12: D<7>
3: DQ6_OBUF.FBK.LFBK 8: D<1> 13: G
4: DQ7_OBUF.FBK.LFBK 9: D<2> 14: REST
5: DQ8_OBUF.FBK.LFBK 10: D<3> 15: WR
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ5 .X....XXXXXXXXX......................... 10 10
DQ9 .....XXXXXXXXXX......................... 10 10
DQ6 ..X...XXXXXXXXX......................... 10 10
DQ7 ...X..XXXXXXXXX......................... 10 10
DQ8 ....X.XXXXXXXXX......................... 10 10
DQ4 X.....XXXXXXXXX......................... 10 10
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
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