counter8.xml
来自「xilinx xc9572 cpld 实现的伺服电机控制器」· XML 代码 · 共 4 行 · 第 1/4 页
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<document><ascFile>counter8.rpt</ascFile><devFile>D:/Xilinx/xc9500/data/xc9572.chp</devFile><mfdFile>counter8.mfd</mfdFile><htmlFile logo="xc9500_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="TQ100" date=" 4- 7-2006" time=" 2:54PM" speed="-10" design="counter8" device="XC9572" status="1" eqnType="1" version="1.0" statusStr="Successful" swVersion="G.35"/><inputs id="CCLK"/><inputs id="CLR"/><inputs id="L"/><inputs id="Din0_SPECSIG"/><inputs id="CE"/><inputs id="UP"/><inputs id="Din10_SPECSIG"/><inputs id="Din11_SPECSIG"/><inputs id="Din1_SPECSIG"/><inputs id="Din2_SPECSIG"/><inputs id="Din3_SPECSIG"/><inputs id="Din4_SPECSIG"/><inputs id="Din5_SPECSIG"/><inputs id="Din6_SPECSIG"/><inputs id="Din7_SPECSIG"/><inputs id="Din8_SPECSIG"/><inputs id="Din9_SPECSIG"/><inputs id="Din12_SPECSIG"/><pin id="FB1_MC1_PIN16" pinnum="16"/><pin id="FB1_MC2_PIN13" use="I" pinnum="13" signal="Din9_SPECSIG"/><pin id="FB1_MC3_PIN18" use="O" slew="SLOW" pinnum="18" signal="Qout11_SPECSIG"/><pin id="FB1_MC4_PIN20" pinnum="20"/><pin id="FB1_MC5_PIN14" use="I" pinnum="14" signal="Din1_SPECSIG"/><pin id="FB1_MC6_PIN15" pinnum="15"/><pin id="FB1_MC7_PIN25" use="b_SPECSIG" pinnum="25"/><pin id="FB1_MC8_PIN17" use="O" slew="SLOW" pinnum="17" signal="Qout12_SPECSIG"/><pin id="FB1_MC9_PIN22" pinnum="22"/><pin id="FB1_MC10_PIN28" use="I" pinnum="28" signal="Din2_SPECSIG"/><pin id="FB1_MC11_PIN23" use="b_SPECSIG" pinnum="23"/><pin id="FB1_MC12_PIN33" use="O" slew="SLOW" pinnum="33" signal="Qout1_SPECSIG"/><pin id="FB1_MC13_PIN36" pinnum="36"/><pin id="FB1_MC14_PIN27" pinnum="27"/><pin id="FB1_MC15_PIN29" use="I" pinnum="29" signal="Din12_SPECSIG"/><pin id="FB1_MC16_PIN39" use="O" slew="SLOW" pinnum="39" signal="Qout0_SPECSIG"/><pin id="FB1_MC17_PIN30" pinnum="30"/><pin id="FB1_MC18_PIN40" pinnum="40"/><pin id="FB2_MC1_PIN87" pinnum="87"/><pin id="FB2_MC2_PIN94" use="b_SPECSIG" pinnum="94"/><pin id="FB2_MC3_PIN91" use="O" slew="SLOW" pinnum="91" signal="Qout7_SPECSIG"/><pin id="FB2_MC4_PIN93" use="b_SPECSIG" pinnum="93" signal="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/><pin id="FB2_MC5_PIN95" use="I" pinnum="95" signal="CCLK"/><pin id="FB2_MC6_PIN96" use="b_SPECSIG" pinnum="96" signal="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"/><pin id="FB2_MC7_PIN3" use="b_SPECSIG" pinnum="3" signal="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"/><pin id="FB2_MC8_PIN97" use="O" slew="SLOW" pinnum="97" signal="Qout8_SPECSIG"/><pin id="FB2_MC9_PIN99" use="b_SPECSIG" pinnum="99" signal="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"/><pin id="FB2_MC10_PIN1" use="b_SPECSIG" pinnum="1" signal="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"/><pin id="FB2_MC11_PIN4" use="b_SPECSIG" pinnum="4" signal="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG"/><pin id="FB2_MC12_PIN6" use="b_SPECSIG" pinnum="6" signal="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG"/><pin id="FB2_MC13_PIN8" use="b_SPECSIG" pinnum="8" signal="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG"/><pin id="FB2_MC14_PIN9" use="O" slew="SLOW" pinnum="9" signal="Qout9_SPECSIG"/><pin id="FB2_MC15_PIN11" use="I" pinnum="11" signal="UP"/><pin id="FB2_MC16_PIN10" use="b_SPECSIG" pinnum="10" signal="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"/><pin id="FB2_MC17_PIN12" use="I" pinnum="12" signal="Din5_SPECSIG"/><pin id="FB2_MC18_PIN92" use="b_SPECSIG" pinnum="92" signal="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"/><pin id="FB3_MC1_PIN41" pinnum="41"/><pin id="FB3_MC2_PIN32" use="I" pinnum="32" signal="Din11_SPECSIG"/><pin id="FB3_MC3_PIN49" use="O" slew="SLOW" pinnum="49" signal="Qout10_SPECSIG"/><pin id="FB3_MC4_PIN50" pinnum="50"/><pin id="FB3_MC5_PIN35" use="I" pinnum="35" signal="Din3_SPECSIG"/><pin id="FB3_MC6_PIN53" pinnum="53"/><pin id="FB3_MC7_PIN54" use="b_SPECSIG" pinnum="54"/><pin id="FB3_MC8_PIN37" use="O" slew="SLOW" pinnum="37" signal="Qout2_SPECSIG"/><pin id="FB3_MC9_PIN42" use="I" pinnum="42" signal="Din8_SPECSIG"/><pin id="FB3_MC10_PIN60" pinnum="60"/><pin id="FB3_MC11_PIN52" use="I" pinnum="52" signal="Din7_SPECSIG"/><pin id="FB3_MC12_PIN61" use="b_SPECSIG" pinnum="61" signal="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"/><pin id="FB3_MC13_PIN63" use="O" slew="SLOW" pinnum="63" signal="Qout4_SPECSIG"/><pin id="FB3_MC14_PIN55" use="b_SPECSIG" pinnum="55" signal="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"/><pin id="FB3_MC15_PIN56" use="I" pinnum="56" signal="CLR"/><pin id="FB3_MC16_PIN65" use="b_SPECSIG" pinnum="65" signal="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"/><pin id="FB3_MC17_PIN58" use="b_SPECSIG" pinnum="58" signal="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"/><pin id="FB3_MC18_PIN59" use="b_SPECSIG" pinnum="59" signal="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG"/><pin id="FB4_MC1_PIN66" pinnum="66"/><pin id="FB4_MC2_PIN64" use="I" pinnum="64" signal="L"/><pin id="FB4_MC3_PIN71" use="O" slew="SLOW" pinnum="71" signal="Qout3_SPECSIG"/><pin id="FB4_MC4_PIN72" pinnum="72"/><pin id="FB4_MC5_PIN67" use="I" pinnum="67" signal="Din4_SPECSIG"/><pin id="FB4_MC6_PIN76" pinnum="76"/><pin id="FB4_MC7_PIN77" use="b_SPECSIG" pinnum="77"/><pin id="FB4_MC8_PIN68" use="O" slew="SLOW" pinnum="68" signal="Qout5_SPECSIG"/><pin id="FB4_MC9_PIN70" pinnum="70"/><pin id="FB4_MC10_PIN81" pinnum="81"/><pin id="FB4_MC11_PIN74" use="I" pinnum="74" signal="CE"/><pin id="FB4_MC12_PIN82" use="b_SPECSIG" pinnum="82"/><pin id="FB4_MC13_PIN85" use="O" slew="SLOW" pinnum="85" signal="Qout6_SPECSIG"/><pin id="FB4_MC14_PIN78" use="I" pinnum="78" signal="Din6_SPECSIG"/><pin id="FB4_MC15_PIN89" use="I" pinnum="89" signal="Din10_SPECSIG"/><pin id="FB4_MC16_PIN86" pinnum="86"/><pin id="FB4_MC17_PIN90" use="I" pinnum="90" signal="Din0_SPECSIG"/><pin id="FB4_MC18_PIN79" pinnum="79"/><fblock id="FB1" pinUse="8" inputUse="15"><macrocell id="FB1_MC1" pin="FB1_MC1_PIN16"/><macrocell id="FB1_MC2" pin="FB1_MC2_PIN13"><pterms pt1="FB1_2_1"/></macrocell><macrocell id="FB1_MC3" pin="FB1_MC3_PIN18" sigUse="8" signal="Qout11_SPECSIG"><pterms pt1="FB1_3_1" pt2="FB1_3_2" pt3="FB1_3_3" pt4="FB1_3_4" pt5="FB1_3_5"/></macrocell><macrocell id="FB1_MC4" pin="FB1_MC4_PIN20"/><macrocell id="FB1_MC5" pin="FB1_MC5_PIN14"/><macrocell id="FB1_MC6" pin="FB1_MC6_PIN15"/><macrocell id="FB1_MC7" pin="FB1_MC7_PIN25"><pterms pt1="FB1_7_1"/></macrocell><macrocell id="FB1_MC8" pin="FB1_MC8_PIN17" sigUse="9" signal="Qout12_SPECSIG"><pterms pt1="FB1_8_1" pt2="FB1_8_2" pt3="FB1_8_3" pt4="FB1_8_4" pt5="FB1_8_5"/></macrocell><macrocell id="FB1_MC9" pin="FB1_MC9_PIN22"/><macrocell id="FB1_MC10" pin="FB1_MC10_PIN28"/><macrocell id="FB1_MC11" pin="FB1_MC11_PIN23"><pterms pt1="FB1_11_1"/></macrocell><macrocell id="FB1_MC12" pin="FB1_MC12_PIN33" sigUse="8" signal="Qout1_SPECSIG"><pterms pt1="FB1_12_1" pt2="FB1_12_2" pt3="FB1_12_3" pt4="FB1_12_4" pt5="FB1_12_5"/></macrocell><macrocell id="FB1_MC13" pin="FB1_MC13_PIN36"/><macrocell id="FB1_MC14" pin="FB1_MC14_PIN27"/><macrocell id="FB1_MC15" pin="FB1_MC15_PIN29"/><macrocell id="FB1_MC16" pin="FB1_MC16_PIN39" sigUse="6" signal="Qout0_SPECSIG"><pterms pt1="FB1_16_1" pt2="FB1_16_2" pt3="FB1_16_3" pt4="FB1_16_4" pt5="FB1_16_5"/></macrocell><macrocell id="FB1_MC17" pin="FB1_MC17_PIN30"/><macrocell id="FB1_MC18" pin="FB1_MC18_PIN40"/><fbinput id="FB1_I1" signal="CCLK"/><fbinput id="FB1_I2" signal="CE"/><fbinput id="FB1_I3" signal="CLR"/><fbinput id="FB1_I4" signal="Din0_SPECSIG"/><fbinput id="FB1_I5" signal="Din11_SPECSIG"/><fbinput id="FB1_I6" signal="Din12_SPECSIG"/><fbinput id="FB1_I7" signal="Din1_SPECSIG"/><fbinput id="FB1_I8" signal="L"/><fbinput id="FB1_I9" signal="Qout0_SPECSIG"/><fbinput id="FB1_I10" signal="Qout11_SPECSIG"/><fbinput id="FB1_I11" signal="Qout12_SPECSIG"/><fbinput id="FB1_I12" signal="Qout1_SPECSIG"/><fbinput id="FB1_I13" signal="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG"/><fbinput id="FB1_I14" signal="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"/><fbinput id="FB1_I15" signal="UP"/><pterm id="FB1_2_1"><signal id="Qout11_SPECSIG"/><signal id="L"/><signal id="Din11_SPECSIG" negated="ON"/></pterm><pterm id="FB1_3_1"><signal id="Qout11_SPECSIG" negated="ON"/><signal id="L"/><signal id="Din11_SPECSIG"/></pterm><pterm id="FB1_3_2"><signal id="UP"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"/></pterm><pterm id="FB1_3_3"><signal id="UP" negated="ON"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG" negated="ON"/></pterm><pterm id="FB1_3_4"><signal id="CLR"/></pterm><pterm id="FB1_3_5"><signal id="CCLK"/></pterm><pterm id="FB1_7_1"><signal id="Qout12_SPECSIG"/><signal id="L"/><signal id="Din12_SPECSIG" negated="ON"/></pterm><pterm id="FB1_8_1"><signal id="Qout12_SPECSIG" negated="ON"/><signal id="L"/><signal id="Din12_SPECSIG"/></pterm><pterm id="FB1_8_2"><signal id="Qout11_SPECSIG"/><signal id="UP"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"/></pterm><pterm id="FB1_8_3"><signal id="Qout11_SPECSIG" negated="ON"/><signal id="UP" negated="ON"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG" negated="ON"/></pterm><pterm id="FB1_8_4"><signal id="CLR"/></pterm><pterm id="FB1_8_5"><signal id="CCLK"/></pterm><pterm id="FB1_11_1"><signal id="Qout0_SPECSIG"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB1_12_1"><signal id="L"/><signal id="Din1_SPECSIG"/></pterm><pterm id="FB1_12_2"><signal id="Qout1_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB1_12_3"><signal id="Qout0_SPECSIG" negated="ON"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB1_12_4"><signal id="CLR"/></pterm><pterm id="FB1_12_5"><signal id="CCLK"/></pterm><pterm id="FB1_16_1"><signal id="L"/><signal id="Din0_SPECSIG"/></pterm><pterm id="FB1_16_2"><signal id="Qout0_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB1_16_3"><signal id="Qout0_SPECSIG" negated="ON"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/></pterm><pterm id="FB1_16_4"><signal id="CLR"/></pterm><pterm id="FB1_16_5"><signal id="CCLK"/></pterm><equation id="Qout11_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_3_1"/><eq_pterm ptindx="FB1_3_2"/><eq_pterm ptindx="FB1_3_3"/><eq_pterm import="1" ptindx="FB1_2_1"/></d2><clk><eq_pterm ptindx="FB1_3_5"/></clk><reset><eq_pterm ptindx="FB1_3_4"/></reset><prld ptindx="GND"/></equation><equation id="Qout12_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB1_8_1"/><eq_pterm ptindx="FB1_8_2"/><eq_pterm ptindx="FB1_8_3"/><eq_pterm import="1" ptindx="FB1_7_1"/></d2><clk><eq_pterm ptindx="FB1_8_5"/></clk><reset><eq_pterm ptindx="FB1_8_4"/></reset><prld ptindx="GND"/></equation><equation id="Qout1_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB1_12_1"/><eq_pterm ptindx="FB1_12_2"/><eq_pterm ptindx="FB1_12_3"/><eq_pterm import="1" ptindx="FB1_11_1"/></d2><clk><eq_pterm ptindx="FB1_12_5"/></clk><reset><eq_pterm ptindx="FB1_12_4"/></reset><prld ptindx="GND"/></equation><equation id="Qout0_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB1_16_1"/><eq_pterm ptindx="FB1_16_2"/><eq_pterm ptindx="FB1_16_3"/></d2><clk><eq_pterm ptindx="FB1_16_5"/></clk><reset><eq_pterm ptindx="FB1_16_4"/></reset><prld ptindx="GND"/></equation></fblock><fblock id="FB2" pinUse="6" inputUse="28"><macrocell id="FB2_MC1" pin="FB2_MC1_PIN87"/><macrocell id="FB2_MC2" pin="FB2_MC2_PIN94"><pterms pt1="FB2_2_1"/></macrocell><macrocell id="FB2_MC3" pin="FB2_MC3_PIN91" sigUse="8" signal="Qout7_SPECSIG"><pterms pt1="FB2_3_1" pt2="FB2_3_2" pt3="FB2_3_3" pt4="FB2_3_4" pt5="FB2_3_5"/></macrocell><macrocell id="FB2_MC4" pin="FB2_MC4_PIN93" sigUse="3" signal="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"><pterms pt1="FB2_4_1" pt2="FB2_4_2"/></macrocell><macrocell id="FB2_MC5" pin="FB2_MC5_PIN95" sigUse="3" signal="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG"><pterms pt1="FB2_5_1" pt2="FB2_5_2"/></macrocell><macrocell id="FB2_MC6" pin="FB2_MC6_PIN96" sigUse="3" signal="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"><pterms pt1="FB2_6_1" pt2="FB2_6_2"/></macrocell><macrocell id="FB2_MC7" pin="FB2_MC7_PIN3" sigUse="3" signal="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"><pterms pt1="FB2_7_1" pt2="FB2_7_2" pt3="FB2_7_3"/></macrocell><macrocell id="FB2_MC8" pin="FB2_MC8_PIN97" sigUse="8" signal="Qout8_SPECSIG"><pterms pt1="FB2_8_1" pt2="FB2_8_2" pt3="FB2_8_3" pt4="FB2_8_4" pt5="FB2_8_5"/></macrocell><macrocell id="FB2_MC9" pin="FB2_MC9_PIN99" sigUse="3" signal="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"><pterms pt1="FB2_9_1" pt2="FB2_9_2"/></macrocell><macrocell id="FB2_MC10" pin="FB2_MC10_PIN1" sigUse="3" signal="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"><pterms pt1="FB2_10_1" pt2="FB2_10_2"/></macrocell><macrocell id="FB2_MC11" pin="FB2_MC11_PIN4" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG"><pterms pt1="FB2_11_1" pt2="FB2_11_2"/></macrocell><macrocell id="FB2_MC12" pin="FB2_MC12_PIN6" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG"><pterms pt1="FB2_12_1" pt2="FB2_12_2"/></macrocell><macrocell id="FB2_MC13" pin="FB2_MC13_PIN8" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG"><pterms pt1="FB2_13_1" pt2="FB2_13_2" pt3="FB2_13_3"/></macrocell><macrocell id="FB2_MC14" pin="FB2_MC14_PIN9" sigUse="8" signal="Qout9_SPECSIG"><pterms pt1="FB2_14_1" pt2="FB2_14_2" pt3="FB2_14_3" pt4="FB2_14_4" pt5="FB2_14_5"/></macrocell><macrocell id="FB2_MC15" pin="FB2_MC15_PIN11" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG"><pterms pt1="FB2_15_1" pt2="FB2_15_2"/></macrocell><macrocell id="FB2_MC16" pin="FB2_MC16_PIN10" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"><pterms pt1="FB2_16_1" pt2="FB2_16_2"/></macrocell><macrocell id="FB2_MC17" pin="FB2_MC17_PIN12" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG"><pterms pt1="FB2_17_1" pt2="FB2_17_2"/></macrocell><macrocell id="FB2_MC18" pin="FB2_MC18_PIN92" sigUse="3" signal="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"><pterms pt1="FB2_18_1" pt2="FB2_18_2" pt3="FB2_18_3"/></macrocell><fbinput id="FB2_I1" signal="CCLK"/><fbinput id="FB2_I2" signal="CE"/><fbinput id="FB2_I3" signal="CLR"/><fbinput id="FB2_I4" signal="Din7_SPECSIG"/><fbinput id="FB2_I5" signal="Din8_SPECSIG"/><fbinput id="FB2_I6" signal="Din9_SPECSIG"/><fbinput id="FB2_I7" signal="L"/><fbinput id="FB2_I8" signal="Qout0_SPECSIG"/><fbinput id="FB2_I9" signal="Qout10_SPECSIG"/><fbinput id="FB2_I10" signal="Qout1_SPECSIG"/><fbinput id="FB2_I11" signal="Qout2_SPECSIG"/><fbinput id="FB2_I12" signal="Qout3_SPECSIG"/><fbinput id="FB2_I13" signal="Qout7_SPECSIG"/><fbinput id="FB2_I14" signal="Qout8_SPECSIG"/><fbinput id="FB2_I15" signal="Qout9_SPECSIG"/><fbinput id="FB2_I16" signal="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG"/><fbinput id="FB2_I17" signal="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"/><fbinput id="FB2_I18" signal="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG"/><fbinput id="FB2_I19" signal="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG"/><fbinput id="FB2_I20" signal="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG"/><fbinput id="FB2_I21" signal="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG"/><fbinput id="FB2_I22" signal="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"/><fbinput id="FB2_I23" signal="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"/><fbinput id="FB2_I24" signal="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"/><fbinput id="FB2_I25" signal="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"/><fbinput id="FB2_I26" signal="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG"/><fbinput id="FB2_I27" signal="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/><fbinput id="FB2_I28" signal="UP"/><pterm id="FB2_2_1"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_3_1"><signal id="L"/><signal id="Din7_SPECSIG"/></pterm><pterm id="FB2_3_2"><signal id="Qout7_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB2_3_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_3_4"><signal id="CLR"/></pterm><pterm id="FB2_3_5"><signal id="CCLK"/></pterm><pterm id="FB2_4_1"><signal id="Qout9_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_4_2"><signal id="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_5_1"><signal id="Qout8_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_5_2"><signal id="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_6_1"><signal id="Qout7_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_6_2"><signal id="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_7_1"><signal id="Qout3_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_7_2"><signal id="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_7_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_8_1"><signal id="L"/><signal id="Din8_SPECSIG"/></pterm><pterm id="FB2_8_2"><signal id="Qout8_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB2_8_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_8_4"><signal id="CLR"/></pterm><pterm id="FB2_8_5"><signal id="CCLK"/></pterm><pterm id="FB2_9_1"><signal id="Qout2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_9_2"><signal id="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_10_1"><signal id="Qout0_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_10_2"><signal id="UP" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_11_1"><signal id="UP"/></pterm><pterm id="FB2_11_2"><signal id="Qout9_SPECSIG"/></pterm><pterm id="FB2_12_1"><signal id="UP"/></pterm><pterm id="FB2_12_2"><signal id="Qout8_SPECSIG"/></pterm><pterm id="FB2_13_1"><signal id="UP"/></pterm><pterm id="FB2_13_2"><signal id="Qout7_SPECSIG"/></pterm><pterm id="FB2_13_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB2_14_1"><signal id="L"/><signal id="Din9_SPECSIG"/></pterm><pterm id="FB2_14_2"><signal id="Qout9_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB2_14_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB2_14_4"><signal id="CLR"/></pterm><pterm id="FB2_14_5"><signal id="CCLK"/></pterm><pterm id="FB2_15_1"><signal id="UP"/></pterm><pterm id="FB2_15_2"><signal id="Qout3_SPECSIG"/></pterm><pterm id="FB2_16_1"><signal id="UP"/></pterm><pterm id="FB2_16_2"><signal id="Qout2_SPECSIG"/></pterm><pterm id="FB2_17_1"><signal id="UP"/></pterm><pterm id="FB2_17_2"><signal id="Qout1_SPECSIG"/></pterm><pterm id="FB2_18_1"><signal id="Qout10_SPECSIG"/><signal id="UP" negated="ON"/></pterm><pterm id="FB2_18_2"><signal id="Qout10_SPECSIG"/><signal id="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/></pterm><pterm id="FB2_18_3"><signal id="UP" negated="ON"/><signal id="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/></pterm><equation id="Qout7_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_3_1"/><eq_pterm ptindx="FB2_3_2"/><eq_pterm ptindx="FB2_3_3"/><eq_pterm import="1" ptindx="FB2_2_1"/></d2><clk><eq_pterm ptindx="FB2_3_5"/></clk><reset><eq_pterm ptindx="FB2_3_4"/></reset><prld ptindx="GND"/></equation><equation id="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_4_1"/><eq_pterm ptindx="FB2_4_2"/></d2></equation><equation id="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_5_1"/><eq_pterm ptindx="FB2_5_2"/></d2></equation><equation id="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_6_1"/><eq_pterm ptindx="FB2_6_2"/></d2></equation><equation id="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_7_1"/><eq_pterm ptindx="FB2_7_2"/></d2></equation><equation id="Qout8_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_8_1"/><eq_pterm ptindx="FB2_8_2"/><eq_pterm ptindx="FB2_8_3"/><eq_pterm import="1" ptindx="FB2_7_3"/></d2><clk><eq_pterm ptindx="FB2_8_5"/></clk><reset><eq_pterm ptindx="FB2_8_4"/></reset><prld ptindx="GND"/></equation><equation id="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_9_1"/><eq_pterm ptindx="FB2_9_2"/></d2></equation><equation id="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_10_1"/><eq_pterm ptindx="FB2_10_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB2_11_1"/></d1><d2><eq_pterm ptindx="FB2_11_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB2_12_1"/></d1><d2><eq_pterm ptindx="FB2_12_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB2_13_1"/></d1><d2><eq_pterm ptindx="FB2_13_2"/></d2></equation><equation id="Qout9_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB2_14_1"/><eq_pterm ptindx="FB2_14_2"/><eq_pterm ptindx="FB2_14_3"/><eq_pterm import="1" ptindx="FB2_13_3"/></d2><clk><eq_pterm ptindx="FB2_14_5"/></clk><reset><eq_pterm ptindx="FB2_14_4"/></reset><prld ptindx="GND"/></equation><equation id="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB2_15_1"/></d1><d2><eq_pterm ptindx="FB2_15_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB2_16_1"/></d1><d2><eq_pterm ptindx="FB2_16_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB2_17_1"/></d1><d2><eq_pterm ptindx="FB2_17_2"/></d2></equation><equation id="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB2_18_1"/><eq_pterm ptindx="FB2_18_2"/><eq_pterm ptindx="FB2_18_3"/></d2></equation></fblock><fblock id="FB3" pinUse="8" inputUse="22"><macrocell id="FB3_MC1" pin="FB3_MC1_PIN41"/><macrocell id="FB3_MC2" pin="FB3_MC2_PIN32"><pterms pt1="FB3_2_1"/></macrocell><macrocell id="FB3_MC3" pin="FB3_MC3_PIN49" sigUse="8" signal="Qout10_SPECSIG"><pterms pt1="FB3_3_1" pt2="FB3_3_2" pt3="FB3_3_3" pt4="FB3_3_4" pt5="FB3_3_5"/></macrocell><macrocell id="FB3_MC4" pin="FB3_MC4_PIN50"/><macrocell id="FB3_MC5" pin="FB3_MC5_PIN35"/><macrocell id="FB3_MC6" pin="FB3_MC6_PIN53"/><macrocell id="FB3_MC7" pin="FB3_MC7_PIN54"><pterms pt1="FB3_7_1"/></macrocell><macrocell id="FB3_MC8" pin="FB3_MC8_PIN37" sigUse="8" signal="Qout2_SPECSIG"><pterms pt1="FB3_8_1" pt2="FB3_8_2" pt3="FB3_8_3" pt4="FB3_8_4" pt5="FB3_8_5"/></macrocell><macrocell id="FB3_MC9" pin="FB3_MC9_PIN42"/><macrocell id="FB3_MC10" pin="FB3_MC10_PIN60"/><macrocell id="FB3_MC11" pin="FB3_MC11_PIN52"/><macrocell id="FB3_MC12" pin="FB3_MC12_PIN61" sigUse="3" signal="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"><pterms pt1="FB3_12_1" pt2="FB3_12_2" pt3="FB3_12_3"/></macrocell><macrocell id="FB3_MC13" pin="FB3_MC13_PIN63" sigUse="8" signal="Qout4_SPECSIG"><pterms pt1="FB3_13_1" pt2="FB3_13_2" pt3="FB3_13_3" pt4="FB3_13_4" pt5="FB3_13_5"/></macrocell><macrocell id="FB3_MC14" pin="FB3_MC14_PIN55" sigUse="3" signal="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"><pterms pt1="FB3_14_1" pt2="FB3_14_2"/></macrocell><macrocell id="FB3_MC15" pin="FB3_MC15_PIN56" sigUse="3" signal="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"><pterms pt1="FB3_15_1" pt2="FB3_15_2"/></macrocell><macrocell id="FB3_MC16" pin="FB3_MC16_PIN65" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"><pterms pt1="FB3_16_1" pt2="FB3_16_2"/></macrocell><macrocell id="FB3_MC17" pin="FB3_MC17_PIN58" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"><pterms pt1="FB3_17_1" pt2="FB3_17_2"/></macrocell><macrocell id="FB3_MC18" pin="FB3_MC18_PIN59" sigUse="2" signal="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG"><pterms pt1="FB3_18_1" pt2="FB3_18_2"/></macrocell><fbinput id="FB3_I1" signal="CCLK"/><fbinput id="FB3_I2" signal="CE"/><fbinput id="FB3_I3" signal="CLR"/><fbinput id="FB3_I4" signal="Din10_SPECSIG"/><fbinput id="FB3_I5" signal="Din2_SPECSIG"/><fbinput id="FB3_I6" signal="Din4_SPECSIG"/><fbinput id="FB3_I7" signal="L"/><fbinput id="FB3_I8" signal="Qout10_SPECSIG"/><fbinput id="FB3_I9" signal="Qout2_SPECSIG"/><fbinput id="FB3_I10" signal="Qout4_SPECSIG"/><fbinput id="FB3_I11" signal="Qout5_SPECSIG"/><fbinput id="FB3_I12" signal="Qout6_SPECSIG"/><fbinput id="FB3_I13" signal="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"/><fbinput id="FB3_I14" signal="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG"/><fbinput id="FB3_I15" signal="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"/><fbinput id="FB3_I16" signal="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"/><fbinput id="FB3_I17" signal="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"/><fbinput id="FB3_I18" signal="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"/><fbinput id="FB3_I19" signal="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"/><fbinput id="FB3_I20" signal="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"/><fbinput id="FB3_I21" signal="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/><fbinput id="FB3_I22" signal="UP"/><pterm id="FB3_2_1"><signal id="Qout10_SPECSIG"/><signal id="L"/><signal id="Din10_SPECSIG" negated="ON"/></pterm><pterm id="FB3_3_1"><signal id="Qout10_SPECSIG" negated="ON"/><signal id="L"/><signal id="Din10_SPECSIG"/></pterm><pterm id="FB3_3_2"><signal id="UP"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/></pterm><pterm id="FB3_3_3"><signal id="UP" negated="ON"/><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG" negated="ON"/></pterm><pterm id="FB3_3_4"><signal id="CLR"/></pterm><pterm id="FB3_3_5"><signal id="CCLK"/></pterm><pterm id="FB3_7_1"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB3_8_1"><signal id="L"/><signal id="Din2_SPECSIG"/></pterm><pterm id="FB3_8_2"><signal id="Qout2_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB3_8_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB3_8_4"><signal id="CLR"/></pterm><pterm id="FB3_8_5"><signal id="CCLK"/></pterm><pterm id="FB3_12_1"><signal id="Qout6_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB3_12_2"><signal id="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB3_12_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB3_13_1"><signal id="L"/><signal id="Din4_SPECSIG"/></pterm><pterm id="FB3_13_2"><signal id="Qout4_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB3_13_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB3_13_4"><signal id="CLR"/></pterm><pterm id="FB3_13_5"><signal id="CCLK"/></pterm><pterm id="FB3_14_1"><signal id="Qout5_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB3_14_2"><signal id="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB3_15_1"><signal id="Qout4_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB3_15_2"><signal id="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB3_16_1"><signal id="UP"/></pterm><pterm id="FB3_16_2"><signal id="Qout6_SPECSIG"/></pterm><pterm id="FB3_17_1"><signal id="UP"/></pterm><pterm id="FB3_17_2"><signal id="Qout5_SPECSIG"/></pterm><pterm id="FB3_18_1"><signal id="UP"/></pterm><pterm id="FB3_18_2"><signal id="Qout4_SPECSIG"/></pterm><equation id="Qout10_SPECSIG" regUse="T"><d2><eq_pterm ptindx="FB3_3_1"/><eq_pterm ptindx="FB3_3_2"/><eq_pterm ptindx="FB3_3_3"/><eq_pterm import="1" ptindx="FB3_2_1"/></d2><clk><eq_pterm ptindx="FB3_3_5"/></clk><reset><eq_pterm ptindx="FB3_3_4"/></reset><prld ptindx="GND"/></equation><equation id="Qout2_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB3_8_1"/><eq_pterm ptindx="FB3_8_2"/><eq_pterm ptindx="FB3_8_3"/><eq_pterm import="1" ptindx="FB3_7_1"/></d2><clk><eq_pterm ptindx="FB3_8_5"/></clk><reset><eq_pterm ptindx="FB3_8_4"/></reset><prld ptindx="GND"/></equation><equation id="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB3_12_1"/><eq_pterm ptindx="FB3_12_2"/></d2></equation><equation id="Qout4_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB3_13_1"/><eq_pterm ptindx="FB3_13_2"/><eq_pterm ptindx="FB3_13_3"/><eq_pterm import="1" ptindx="FB3_12_3"/></d2><clk><eq_pterm ptindx="FB3_13_5"/></clk><reset><eq_pterm ptindx="FB3_13_4"/></reset><prld ptindx="GND"/></equation><equation id="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB3_14_1"/><eq_pterm ptindx="FB3_14_2"/></d2></equation><equation id="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"><d2><eq_pterm ptindx="FB3_15_1"/><eq_pterm ptindx="FB3_15_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB3_16_1"/></d1><d2><eq_pterm ptindx="FB3_16_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB3_17_1"/></d1><d2><eq_pterm ptindx="FB3_17_2"/></d2></equation><equation id="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG" negated="ON"><d1><eq_pterm ptindx="FB3_18_1"/></d1><d2><eq_pterm ptindx="FB3_18_2"/></d2></equation></fblock><fblock id="FB4" pinUse="9" inputUse="16"><macrocell id="FB4_MC1" pin="FB4_MC1_PIN66"/><macrocell id="FB4_MC2" pin="FB4_MC2_PIN64"><pterms pt1="FB4_2_1"/></macrocell><macrocell id="FB4_MC3" pin="FB4_MC3_PIN71" sigUse="8" signal="Qout3_SPECSIG"><pterms pt1="FB4_3_1" pt2="FB4_3_2" pt3="FB4_3_3" pt4="FB4_3_4" pt5="FB4_3_5"/></macrocell><macrocell id="FB4_MC4" pin="FB4_MC4_PIN72"/><macrocell id="FB4_MC5" pin="FB4_MC5_PIN67"/><macrocell id="FB4_MC6" pin="FB4_MC6_PIN76"/><macrocell id="FB4_MC7" pin="FB4_MC7_PIN77"><pterms pt1="FB4_7_1"/></macrocell><macrocell id="FB4_MC8" pin="FB4_MC8_PIN68" sigUse="8" signal="Qout5_SPECSIG"><pterms pt1="FB4_8_1" pt2="FB4_8_2" pt3="FB4_8_3" pt4="FB4_8_4" pt5="FB4_8_5"/></macrocell><macrocell id="FB4_MC9" pin="FB4_MC9_PIN70"/><macrocell id="FB4_MC10" pin="FB4_MC10_PIN81"/><macrocell id="FB4_MC11" pin="FB4_MC11_PIN74"/><macrocell id="FB4_MC12" pin="FB4_MC12_PIN82"><pterms pt1="FB4_12_1"/></macrocell><macrocell id="FB4_MC13" pin="FB4_MC13_PIN85" sigUse="8" signal="Qout6_SPECSIG"><pterms pt1="FB4_13_1" pt2="FB4_13_2" pt3="FB4_13_3" pt4="FB4_13_4" pt5="FB4_13_5"/></macrocell><macrocell id="FB4_MC14" pin="FB4_MC14_PIN78"/><macrocell id="FB4_MC15" pin="FB4_MC15_PIN89"/><macrocell id="FB4_MC16" pin="FB4_MC16_PIN86"/><macrocell id="FB4_MC17" pin="FB4_MC17_PIN90"/><macrocell id="FB4_MC18" pin="FB4_MC18_PIN79"/><fbinput id="FB4_I1" signal="CCLK"/><fbinput id="FB4_I2" signal="CE"/><fbinput id="FB4_I3" signal="CLR"/><fbinput id="FB4_I4" signal="Din3_SPECSIG"/><fbinput id="FB4_I5" signal="Din5_SPECSIG"/><fbinput id="FB4_I6" signal="Din6_SPECSIG"/><fbinput id="FB4_I7" signal="L"/><fbinput id="FB4_I8" signal="Qout3_SPECSIG"/><fbinput id="FB4_I9" signal="Qout5_SPECSIG"/><fbinput id="FB4_I10" signal="Qout6_SPECSIG"/><fbinput id="FB4_I11" signal="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG"/><fbinput id="FB4_I12" signal="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"/><fbinput id="FB4_I13" signal="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"/><fbinput id="FB4_I14" signal="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"/><fbinput id="FB4_I15" signal="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"/><fbinput id="FB4_I16" signal="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"/><pterm id="FB4_2_1"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB4_3_1"><signal id="L"/><signal id="Din3_SPECSIG"/></pterm><pterm id="FB4_3_2"><signal id="Qout3_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB4_3_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB4_3_4"><signal id="CLR"/></pterm><pterm id="FB4_3_5"><signal id="CCLK"/></pterm><pterm id="FB4_7_1"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB4_8_1"><signal id="L"/><signal id="Din5_SPECSIG"/></pterm><pterm id="FB4_8_2"><signal id="Qout5_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB4_8_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB4_8_4"><signal id="CLR"/></pterm><pterm id="FB4_8_5"><signal id="CCLK"/></pterm><pterm id="FB4_12_1"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"/><signal id="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG" negated="ON"/></pterm><pterm id="FB4_13_1"><signal id="L"/><signal id="Din6_SPECSIG"/></pterm><pterm id="FB4_13_2"><signal id="Qout6_SPECSIG"/><signal id="CE"/><signal id="L" negated="ON"/></pterm><pterm id="FB4_13_3"><signal id="CE" negated="ON"/><signal id="L" negated="ON"/><signal id="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG" negated="ON"/><signal id="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"/></pterm><pterm id="FB4_13_4"><signal id="CLR"/></pterm><pterm id="FB4_13_5"><signal id="CCLK"/></pterm><equation id="Qout3_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB4_3_1"/><eq_pterm ptindx="FB4_3_2"/><eq_pterm ptindx="FB4_3_3"/><eq_pterm import="1" ptindx="FB4_2_1"/></d2><clk><eq_pterm ptindx="FB4_3_5"/></clk><reset><eq_pterm ptindx="FB4_3_4"/></reset><prld ptindx="GND"/></equation><equation id="Qout5_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB4_8_1"/><eq_pterm ptindx="FB4_8_2"/><eq_pterm ptindx="FB4_8_3"/><eq_pterm import="1" ptindx="FB4_7_1"/></d2><clk><eq_pterm ptindx="FB4_8_5"/></clk><reset><eq_pterm ptindx="FB4_8_4"/></reset><prld ptindx="GND"/></equation><equation id="Qout6_SPECSIG" regUse="D"><d2><eq_pterm ptindx="FB4_13_1"/><eq_pterm ptindx="FB4_13_2"/><eq_pterm ptindx="FB4_13_3"/><eq_pterm import="1" ptindx="FB4_12_1"/></d2><clk><eq_pterm ptindx="FB4_13_5"/></clk><reset><eq_pterm ptindx="FB4_13_4"/></reset><prld ptindx="GND"/></equation></fblock><vcc/><gnd/><compOpts loc="ON" uim="ON" part="xc9572-10-TQ100" prld="FPGA" slew="SLOW" mlopt="ON" power="STD" gsropt="OFF" gtsopt="OFF" inputs="36" keepio="OFF" pinfbk="OFF" pterms="90" unused="ON" exhaust="OFF" gclkopt="OFF" wysiwyg="OFF" ignorets="OFF" localfbk="OFF" optimize="DENSITY"/><specSig value="Din<0>" signal="Din0_SPECSIG"/><specSig value="Din<10>" signal="Din10_SPECSIG"/><specSig value="Din<11>" signal="Din11_SPECSIG"/><specSig value="Din<1>" signal="Din1_SPECSIG"/><specSig value="Din<2>" signal="Din2_SPECSIG"/><specSig value="Din<3>" signal="Din3_SPECSIG"/><specSig value="Din<4>" signal="Din4_SPECSIG"/><specSig value="Din<5>" signal="Din5_SPECSIG"/><specSig value="Din<6>" signal="Din6_SPECSIG"/><specSig value="Din<7>" signal="Din7_SPECSIG"/><specSig value="Din<8>" signal="Din8_SPECSIG"/><specSig value="Din<9>" signal="Din9_SPECSIG"/><specSig value="Din<12>" signal="Din12_SPECSIG"/><specSig value="Qout<11>" signal="Qout11_SPECSIG"/><specSig value="(b)" signal="b_SPECSIG"/><specSig value="Qout<12>" signal="Qout12_SPECSIG"/><specSig value="Qout<1>" signal="Qout1_SPECSIG"/><specSig value="Qout<0>" signal="Qout0_SPECSIG"/><specSig value="Qout<7>" signal="Qout7_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2" signal="Temp_Maddsub__n0000__n00650Temp_Maddsub__n0000__n0065<0>_D2_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2" signal="Temp_Maddsub__n0000__n00610Temp_Maddsub__n0000__n0061<0>_D2_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2" signal="Temp_Maddsub__n0000__n00530Temp_Maddsub__n0000__n0053<0>_D2_SPECSIG"/><specSig value="Qout<8>" signal="Qout8_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2" signal="Temp_Maddsub__n0000__n00510Temp_Maddsub__n0000__n0051<0>_D2_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2" signal="Temp_Maddsub__n0000__n00490Temp_Maddsub__n0000__n0049<0>_D2_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result9__n0002<0>Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result8__n0002<0>Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result7__n0002<0>Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D_SPECSIG"/><specSig value="Qout<9>" signal="Qout9_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result2__n0002<0>Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2" signal="Temp_Maddsub__n0000__n00670Temp_Maddsub__n0000__n0067<0>_D2_SPECSIG"/><specSig value="Qout<10>" signal="Qout10_SPECSIG"/><specSig value="Qout<2>" signal="Qout2_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2" signal="Temp_Maddsub__n0000__n00590Temp_Maddsub__n0000__n0059<0>_D2_SPECSIG"/><specSig value="Qout<4>" signal="Qout4_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2" signal="Temp_Maddsub__n0000__n00570Temp_Maddsub__n0000__n0057<0>_D2_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result6__n0002<0>Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result5__n0002<0>Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result4__n0002<0>Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D_SPECSIG"/><specSig value="Qout<3>" signal="Qout3_SPECSIG"/><specSig value="Qout<5>" signal="Qout5_SPECSIG"/><specSig value="Qout<6>" signal="Qout6_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result1__n0002<0>Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2" signal="Temp_Maddsub__n0000__n00630Temp_Maddsub__n0000__n0063<0>_D2_SPECSIG"/><specSig value="Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D" signal="Temp_Maddsub__n0000_Mxor_Result3__n0002<0>Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D_SPECSIG"/><specSig value="Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2" signal="Temp_Maddsub__n0000__n00550Temp_Maddsub__n0000__n0055<0>_D2_SPECSIG"/></document>
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