d5_32e.rpt
来自「xilinx xc9572 cpld 实现的伺服电机控制器」· RPT 代码 · 共 512 行 · 第 1/2 页
RPT
512 行
cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: d5_32e Date: 4- 4-2006, 9:20AM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
24 /72 ( 33%) 24 /360 ( 7%) 0 /72 ( 0%) 30 /72 ( 42%) 24 /144 ( 17%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 6 6 | I/O : 30 36
Output : 24 24 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 30 30
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 0
Non-registered Macrocell driving I/O 24
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 24 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 24 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
Dout<0> 1 6 FB3_1 STD FAST 41 I/O O
Dout<10> 1 6 FB4_1 STD FAST 66 I/O O
Dout<11> 1 6 FB3_4 STD FAST 50 I/O O
Dout<12> 1 6 FB4_4 STD FAST 72 I/O O
Dout<13> 1 6 FB3_7 STD FAST 54 I/O O
Dout<14> 1 6 FB3_10 STD FAST 60 I/O O
Dout<15> 1 6 FB4_7 STD FAST 77 I/O O
Dout<16> 1 6 FB4_10 STD FAST 81 I/O O
Dout<17> 1 6 FB3_13 STD FAST 63 I/O O
Dout<18> 1 6 FB3_16 STD FAST 65 I/O O
Dout<19> 1 6 FB1_13 STD FAST 36 I/O O
Dout<1> 1 6 FB1_1 STD FAST 16 I/O O
Dout<20> 1 6 FB1_4 STD FAST 20 I/O O
Dout<21> 1 6 FB1_7 STD FAST 25 I/O O
Dout<22> 1 6 FB1_10 STD FAST 28 I/O O
Dout<23> 1 6 FB1_16 STD FAST 39 I/O O
Dout<2> 1 6 FB4_13 STD FAST 85 I/O O
Dout<3> 1 6 FB4_16 STD FAST 86 I/O O
Dout<4> 1 6 FB2_17 STD FAST 12 I/O O
Dout<5> 1 6 FB2_5 STD FAST 95 I/O O
Dout<6> 1 6 FB2_8 STD FAST 97 I/O O
Dout<7> 1 6 FB2_10 STD FAST 1 I/O O
Dout<8> 1 6 FB2_14 STD FAST 9 I/O O
Dout<9> 1 6 FB2_2 STD FAST 94 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
A0 FB2_15 11 I/O I
A1 FB3_2 32 I/O I
A2 FB3_15 56 I/O I
A3 FB1_8 17 I/O I
A4 FB4_11 74 I/O I
E FB4_2 64 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 6 6 6 6 6/0 18
FB2 6 6 6 6 6/0 18
FB3 6 6 6 6 6/0 18
FB4 6 6 6 6 6/0 18
---- ----- ----- -----
24 24 24/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
Dout<1> 1 0 0 4 FB1_1 STD 16 I/O O
(unused) 0 0 0 5 FB1_2 13 I/O
(unused) 0 0 0 5 FB1_3 18 I/O
Dout<20> 1 0 0 4 FB1_4 STD 20 I/O O
(unused) 0 0 0 5 FB1_5 14 I/O
(unused) 0 0 0 5 FB1_6 15 I/O
Dout<21> 1 0 0 4 FB1_7 STD 25 I/O O
(unused) 0 0 0 5 FB1_8 17 I/O I
(unused) 0 0 0 5 FB1_9 22 GCK/I/O
Dout<22> 1 0 0 4 FB1_10 STD 28 I/O O
(unused) 0 0 0 5 FB1_11 23 GCK/I/O
(unused) 0 0 0 5 FB1_12 33 I/O
Dout<19> 1 0 0 4 FB1_13 STD 36 I/O O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O
(unused) 0 0 0 5 FB1_15 29 I/O
Dout<23> 1 0 0 4 FB1_16 STD 39 I/O O
(unused) 0 0 0 5 FB1_17 30 I/O
(unused) 0 0 0 5 FB1_18 40 I/O
Signals Used by Logic in Function Block
1: A0 3: A2 5: A4
2: A1 4: A3 6: E
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Dout<1> XXXXXX.................................. 6 6
Dout<20> XXXXXX.................................. 6 6
Dout<21> XXXXXX.................................. 6 6
Dout<22> XXXXXX.................................. 6 6
Dout<19> XXXXXX.................................. 6 6
Dout<23> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
Dout<9> 1 0 0 4 FB2_2 STD 94 I/O O
(unused) 0 0 0 5 FB2_3 91 I/O
(unused) 0 0 0 5 FB2_4 93 I/O
Dout<5> 1 0 0 4 FB2_5 STD 95 I/O O
(unused) 0 0 0 5 FB2_6 96 I/O
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
Dout<6> 1 0 0 4 FB2_8 STD 97 I/O O
(unused) 0 0 0 5 FB2_9 99 GSR/I/O
Dout<7> 1 0 0 4 FB2_10 STD 1 I/O O
(unused) 0 0 0 5 FB2_11 4 GTS/I/O
(unused) 0 0 0 5 FB2_12 6 I/O
(unused) 0 0 0 5 FB2_13 8 I/O
Dout<8> 1 0 0 4 FB2_14 STD 9 I/O O
(unused) 0 0 0 5 FB2_15 11 I/O I
(unused) 0 0 0 5 FB2_16 10 I/O
Dout<4> 1 0 0 4 FB2_17 STD 12 I/O O
(unused) 0 0 0 5 FB2_18 92 I/O
Signals Used by Logic in Function Block
1: A0 3: A2 5: A4
2: A1 4: A3 6: E
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Dout<9> XXXXXX.................................. 6 6
Dout<5> XXXXXX.................................. 6 6
Dout<6> XXXXXX.................................. 6 6
Dout<7> XXXXXX.................................. 6 6
Dout<8> XXXXXX.................................. 6 6
Dout<4> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
Dout<0> 1 0 0 4 FB3_1 STD 41 I/O O
(unused) 0 0 0 5 FB3_2 32 I/O I
(unused) 0 0 0 5 FB3_3 49 I/O
Dout<11> 1 0 0 4 FB3_4 STD 50 I/O O
(unused) 0 0 0 5 FB3_5 35 I/O
(unused) 0 0 0 5 FB3_6 53 I/O
Dout<13> 1 0 0 4 FB3_7 STD 54 I/O O
(unused) 0 0 0 5 FB3_8 37 I/O
(unused) 0 0 0 5 FB3_9 42 I/O
Dout<14> 1 0 0 4 FB3_10 STD 60 I/O O
(unused) 0 0 0 5 FB3_11 52 I/O
(unused) 0 0 0 5 FB3_12 61 I/O
Dout<17> 1 0 0 4 FB3_13 STD 63 I/O O
(unused) 0 0 0 5 FB3_14 55 I/O
(unused) 0 0 0 5 FB3_15 56 I/O I
Dout<18> 1 0 0 4 FB3_16 STD 65 I/O O
(unused) 0 0 0 5 FB3_17 58 I/O
(unused) 0 0 0 5 FB3_18 59 I/O
Signals Used by Logic in Function Block
1: A0 3: A2 5: A4
2: A1 4: A3 6: E
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
Dout<0> XXXXXX.................................. 6 6
Dout<11> XXXXXX.................................. 6 6
Dout<13> XXXXXX.................................. 6 6
Dout<14> XXXXXX.................................. 6 6
Dout<17> XXXXXX.................................. 6 6
Dout<18> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
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