d24wave.vhw

xilinx xc9572 cpld 实现的伺服电机控制器

			END IF;
		END;

		PROCEDURE CHECK_DQ20(
			next_DQ20 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (DQ20 /= next_DQ20) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns DQ20="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ20);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ20);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_DQ21(
			next_DQ21 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (DQ21 /= next_DQ21) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns DQ21="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ21);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ21);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_DQ22(
			next_DQ22 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (DQ22 /= next_DQ22) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns DQ22="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ22);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ22);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_DQ23(
			next_DQ23 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (DQ23 /= next_DQ23) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns DQ23="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ23);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_DQ23);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000000"); --0
		REST <= transport '0';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		REST <= transport '0';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		REST <= transport '0';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		REST <= transport '1';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		REST <= transport '1';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		REST <= transport '1';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		REST <= transport '1';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2100 ns
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2200 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2300 ns
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2400 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2500 ns
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2600 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2700 ns
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2800 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2900 ns
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3000 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3100 ns
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3200 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3300 ns
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3400 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3500 ns
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3600 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3700 ns
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3800 ns
		D <= transport '1';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 700 ns; -- Time=4500 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION dq24_cfg OF d24wave IS
	FOR testbench_arch
	END FOR;
END dq24_cfg;