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来自「xilinx xc9572 cpld 实现的伺服电机控制器」· MFD 代码 · 共 788 行 · 第 1/2 页

MFD
788 行
字号
12
   XLXI_57/Q41<1>.CLK = !XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT.FBK.LFBK;
   XLXI_57/Q41<1>.AR = CLR1;

MACROCELL | 3 | 11 | XLXI_57/Q4<1>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 2 | 6 | 3 | 10
INPUTS | 5 | XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK  | MA0  | MB0  | CLR0  | XLXI_57/Q4<0>.FBK.LFBK
INPUTMC | 3 | 3 | 6 | 1 | 16 | 3 | 12
INPUTP | 2 | 59 | 50
EQ | 4 | 
   XLXI_57/Q4<1>.T = MA0 & !MB0 & XLXI_57/Q4<0>.FBK.LFBK
	# !MA0 & MB0 & !XLXI_57/Q4<0>.FBK.LFBK;
   XLXI_57/Q4<1>.CLK = !XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK;
   XLXI_57/Q4<1>.AR = CLR0;

MACROCELL | 1 | 16 | CLR0
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 5 | 3 | 12 | 3 | 11 | 3 | 9 | 3 | 10 | 1 | 16
INPUTS | 13 | D<1>.PIN  | D<0>.PIN  | CS  | A2  | A1  | A0  | D<4>.PIN  | D<3>.PIN  | D<2>.PIN  | D<7>.PIN  | WR  | RESET  | CLR0.FBK.LFBK
INPUTMC | 1 | 1 | 16
INPUTP | 12 | 11 | 14 | 25 | 26 | 24 | 10 | 12 | 17 | 16 | 15 | 7 | 91
EQ | 6 | 
   CLR0.T = !D<1>.PIN & D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & D<2>.PIN & D<7>.PIN & !CLR0.FBK.LFBK
	# !D<1>.PIN & D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & D<2>.PIN & !D<7>.PIN & CLR0.FBK.LFBK;
   CLR0.CLK = WR;
   CLR0.AR = !RESET;

MACROCELL | 1 | 15 | CLR1
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 5 | 2 | 13 | 2 | 12 | 2 | 10 | 2 | 11 | 1 | 15
INPUTS | 13 | D<1>.PIN  | D<0>.PIN  | CS  | A2  | A1  | A0  | D<4>.PIN  | D<3>.PIN  | D<2>.PIN  | D<7>.PIN  | WR  | RESET  | CLR1.FBK.LFBK
INPUTMC | 1 | 1 | 15
INPUTP | 12 | 11 | 14 | 25 | 26 | 24 | 10 | 12 | 17 | 16 | 15 | 7 | 91
EQ | 6 | 
   CLR1.T = D<1>.PIN & !D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & D<2>.PIN & D<7>.PIN & !CLR1.FBK.LFBK
	# D<1>.PIN & !D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & D<2>.PIN & !D<7>.PIN & CLR1.FBK.LFBK;
   CLR1.CLK = WR;
   CLR1.AR = !RESET;

MACROCELL | 1 | 10 | CSA2
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 0 | 16 | 1 | 10
INPUTS | 13 | D<1>.PIN  | D<0>.PIN  | CS  | A2  | A1  | A0  | D<4>.PIN  | D<3>.PIN  | D<2>.PIN  | D<7>.PIN  | WR  | RESET  | CSA2.FBK.LFBK
INPUTMC | 1 | 1 | 10
INPUTP | 12 | 11 | 14 | 25 | 26 | 24 | 10 | 12 | 17 | 16 | 15 | 7 | 91
EQ | 6 | 
   CSA2.T = D<1>.PIN & !D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & !D<2>.PIN & D<7>.PIN & !CSA2.FBK.LFBK
	# D<1>.PIN & !D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & !D<2>.PIN & !D<7>.PIN & CSA2.FBK.LFBK;
   CSA2.CLK = WR;
   CSA2.AR = !RESET;

MACROCELL | 2 | 11 | XLXI_57/Q41<2>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 1 | 2 | 3
INPUTS | 6 | XLXI_57/Q41<1>.FBK.LFBK  | XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT.FBK.LFBK  | MA1  | MB1  | CLR1  | XLXI_57/Q41<0>.FBK.LFBK
INPUTMC | 4 | 2 | 12 | 2 | 1 | 1 | 15 | 2 | 13
INPUTP | 2 | 57 | 55
EQ | 6 | 
   XLXI_57/Q41<2>.T = MA1 & !MB1 & XLXI_57/Q41<0>.FBK.LFBK & 
	XLXI_57/Q41<1>.FBK.LFBK
	# !MA1 & MB1 & !XLXI_57/Q41<0>.FBK.LFBK & 
	!XLXI_57/Q41<1>.FBK.LFBK;
   XLXI_57/Q41<2>.CLK = !XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT.FBK.LFBK;
   XLXI_57/Q41<2>.AR = CLR1;

MACROCELL | 3 | 10 | XLXI_57/Q4<2>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 1 | 3 | 8
INPUTS | 6 | XLXI_57/Q4<1>.FBK.LFBK  | XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK  | MA0  | MB0  | CLR0  | XLXI_57/Q4<0>.FBK.LFBK
INPUTMC | 4 | 3 | 11 | 3 | 6 | 1 | 16 | 3 | 12
INPUTP | 2 | 59 | 50
EQ | 6 | 
   XLXI_57/Q4<2>.T = MA0 & !MB0 & XLXI_57/Q4<0>.FBK.LFBK & 
	XLXI_57/Q4<1>.FBK.LFBK
	# !MA0 & MB0 & !XLXI_57/Q4<0>.FBK.LFBK & 
	!XLXI_57/Q4<1>.FBK.LFBK;
   XLXI_57/Q4<2>.CLK = !XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK;
   XLXI_57/Q4<2>.AR = CLR0;

MACROCELL | 1 | 13 | CSA1
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 0 | 16 | 1 | 13
INPUTS | 13 | D<1>.PIN  | D<0>.PIN  | CS  | A2  | A1  | A0  | D<4>.PIN  | D<3>.PIN  | D<2>.PIN  | D<7>.PIN  | WR  | RESET  | CSA1.FBK.LFBK
INPUTMC | 1 | 1 | 13
INPUTP | 12 | 11 | 14 | 25 | 26 | 24 | 10 | 12 | 17 | 16 | 15 | 7 | 91
EQ | 6 | 
   CSA1.T = !D<1>.PIN & D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & !D<2>.PIN & D<7>.PIN & !CSA1.FBK.LFBK
	# !D<1>.PIN & D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & !D<2>.PIN & !D<7>.PIN & CSA1.FBK.LFBK;
   CSA1.CLK = WR;
   CSA1.AR = !RESET;

MACROCELL | 2 | 10 | XLXI_57/Q41<3>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 2 | 10 | 2 | 2
INPUTS | 5 | XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT.FBK.LFBK  | MA1  | MB1  | CLR1  | XLXI_57/Q41<3>.FBK.LFBK
INPUTMC | 3 | 2 | 1 | 1 | 15 | 2 | 10
INPUTP | 2 | 57 | 55
EQ | 4 | 
   XLXI_57/Q41<3>.T = MA1 & !MB1 & XLXI_57/Q41<3>.FBK.LFBK
	# !MA1 & MB1 & !XLXI_57/Q41<3>.FBK.LFBK;
   XLXI_57/Q41<3>.CLK = !XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT.FBK.LFBK;
   XLXI_57/Q41<3>.AR = CLR1;

MACROCELL | 3 | 9 | XLXI_57/Q4<3>
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 3 | 9 | 3 | 7
INPUTS | 5 | XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK  | MA0  | MB0  | CLR0  | XLXI_57/Q4<3>.FBK.LFBK
INPUTMC | 3 | 3 | 6 | 1 | 16 | 3 | 9
INPUTP | 2 | 59 | 50
EQ | 4 | 
   XLXI_57/Q4<3>.T = MA0 & !MB0 & XLXI_57/Q4<3>.FBK.LFBK
	# !MA0 & MB0 & !XLXI_57/Q4<3>.FBK.LFBK;
   XLXI_57/Q4<3>.CLK = !XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT.FBK.LFBK;
   XLXI_57/Q4<3>.AR = CLR0;

MACROCELL | 1 | 9 | CS_U
ATTRIBUTES | 4391728 | 0
OUTPUTMC | 2 | 0 | 16 | 1 | 9
INPUTS | 13 | D<1>.PIN  | D<0>.PIN  | CS  | A2  | A1  | A0  | D<4>.PIN  | D<3>.PIN  | D<2>.PIN  | D<7>.PIN  | WR  | RESET  | CS_U.FBK.LFBK
INPUTMC | 1 | 1 | 9
INPUTP | 12 | 11 | 14 | 25 | 26 | 24 | 10 | 12 | 17 | 16 | 15 | 7 | 91
EQ | 6 | 
   CS_U.T = !D<1>.PIN & !D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & D<2>.PIN & D<7>.PIN & !CS_U.FBK.LFBK
	# !D<1>.PIN & !D<0>.PIN & !CS & !A2 & A1 & !A0 & 
	!D<4>.PIN & !D<3>.PIN & D<2>.PIN & !D<7>.PIN & CS_U.FBK.LFBK;
   CS_U.CLK = WR;
   CS_U.AR = !RESET;

MACROCELL | 1 | 11 | ALMR_OBUF
ATTRIBUTES | 264960 | 0
INPUTS | 3 | MR_1<2>  | MR_1<1>  | MR_1<0>
INPUTP | 3 | 65 | 58 | 60
EQ | 1 | 
   !ALMR = !MR_1<2> & !MR_1<1> & !MR_1<0>;

MACROCELL | 2 | 7 | XLXN_8<0>
ATTRIBUTES | 8520624 | 0
OUTPUTMC | 1 | 0 | 0
INPUTS | 2 | XLXI_57/Q4<0>  | RD
INPUTMC | 1 | 3 | 12
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<0>.D = Gnd;
   XLXN_8<0>.CLK = Gnd;
   XLXN_8<0>.AP = XLXI_57/Q4<0> & !RD;
   XLXN_8<0>.AR = !XLXI_57/Q4<0> & !RD;

MACROCELL | 2 | 6 | XLXN_8<1>
ATTRIBUTES | 8520624 | 0
OUTPUTMC | 1 | 0 | 1
INPUTS | 2 | XLXI_57/Q4<1>  | RD
INPUTMC | 1 | 3 | 11
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<1>.D = Gnd;
   XLXN_8<1>.CLK = Gnd;
   XLXN_8<1>.AP = XLXI_57/Q4<1> & !RD;
   XLXN_8<1>.AR = !XLXI_57/Q4<1> & !RD;

MACROCELL | 3 | 8 | XLXN_8<2>
ATTRIBUTES | 8520624 | 0
OUTPUTMC | 1 | 0 | 2
INPUTS | 2 | RD  | XLXI_57/Q4<2>.FBK.LFBK
INPUTMC | 1 | 3 | 10
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<2>.D = Gnd;
   XLXN_8<2>.CLK = Gnd;
   XLXN_8<2>.AP = !RD & XLXI_57/Q4<2>.FBK.LFBK;
   XLXN_8<2>.AR = !RD & !XLXI_57/Q4<2>.FBK.LFBK;

MACROCELL | 3 | 7 | XLXN_8<3>
ATTRIBUTES | 8586160 | 0
OUTPUTMC | 1 | 3 | 15
INPUTS | 2 | RD  | XLXI_57/Q4<3>.FBK.LFBK
INPUTMC | 1 | 3 | 9
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<3>.D = Gnd;
   XLXN_8<3>.CLK = Gnd;
   XLXN_8<3>.AP = !RD & XLXI_57/Q4<3>.FBK.LFBK;
   XLXN_8<3>.AR = !RD & !XLXI_57/Q4<3>.FBK.LFBK;

MACROCELL | 2 | 5 | XLXN_8<4>
ATTRIBUTES | 8520624 | 0
OUTPUTMC | 1 | 3 | 14
INPUTS | 2 | RD  | XLXI_57/Q41<0>.FBK.LFBK
INPUTMC | 1 | 2 | 13
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<4>.D = Gnd;
   XLXN_8<4>.CLK = Gnd;
   XLXN_8<4>.AP = !RD & XLXI_57/Q41<0>.FBK.LFBK;
   XLXN_8<4>.AR = !RD & !XLXI_57/Q41<0>.FBK.LFBK;

MACROCELL | 2 | 4 | XLXN_8<5>
ATTRIBUTES | 8586160 | 0
OUTPUTMC | 1 | 2 | 15
INPUTS | 2 | RD  | XLXI_57/Q41<1>.FBK.LFBK
INPUTMC | 1 | 2 | 12
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<5>.D = Gnd;
   XLXN_8<5>.CLK = Gnd;
   XLXN_8<5>.AP = !RD & XLXI_57/Q41<1>.FBK.LFBK;
   XLXN_8<5>.AR = !RD & !XLXI_57/Q41<1>.FBK.LFBK;

MACROCELL | 2 | 3 | XLXN_8<6>
ATTRIBUTES | 8520624 | 0
OUTPUTMC | 1 | 3 | 13
INPUTS | 2 | RD  | XLXI_57/Q41<2>.FBK.LFBK
INPUTMC | 1 | 2 | 11
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<6>.D = Gnd;
   XLXN_8<6>.CLK = Gnd;
   XLXN_8<6>.AP = !RD & XLXI_57/Q41<2>.FBK.LFBK;
   XLXN_8<6>.AR = !RD & !XLXI_57/Q41<2>.FBK.LFBK;

MACROCELL | 2 | 2 | XLXN_8<7>
ATTRIBUTES | 8586160 | 0
OUTPUTMC | 1 | 2 | 14
INPUTS | 2 | RD  | XLXI_57/Q41<3>.FBK.LFBK
INPUTMC | 1 | 2 | 10
INPUTP | 1 | 21
EQ | 4 | 
   XLXN_8<7>.D = Gnd;
   XLXN_8<7>.CLK = Gnd;
   XLXN_8<7>.AP = !RD & XLXI_57/Q41<3>.FBK.LFBK;
   XLXN_8<7>.AR = !RD & !XLXI_57/Q41<3>.FBK.LFBK;

MACROCELL | 0 | 16 | UART0_OBUF
ATTRIBUTES | 264960 | 0
INPUTS | 6 | CSA2  | CSA1  | CS_U  | MR_2<0>  | MR_2<2>  | MR_2<1>
INPUTMC | 3 | 1 | 10 | 1 | 13 | 1 | 9
INPUTP | 3 | 33 | 47 | 48
EQ | 3 | 
   !UART0 = CSA2 & !CSA1 & CS_U & !MR_2<2>
	# !CSA2 & CSA1 & CS_U & !MR_2<1>
	# !CSA2 & !CSA1 & CS_U & !MR_2<0>;

MACROCELL | 1 | 12 | CLK8_IBUF$BUF0
ATTRIBUTES | 264960 | 0
INPUTS | 1 | CLK8
INPUTP | 1 | 20
EQ | 1 | 
   CLK = CLK8;

MACROCELL | 1 | 14 | INT_L0_IBUF$BUF0
ATTRIBUTES | 264960 | 0
INPUTS | 1 | INT_L0
INPUTP | 1 | 8
EQ | 1 | 
   INT0 = INT_L0;

MACROCELL | 2 | 1 | XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT
ATTRIBUTES | 199424 | 0
OUTPUTMC | 4 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10
INPUTS | 3 | MA1  | MB1  | MC1
INPUTP | 3 | 57 | 55 | 46
EQ | 1 | 
   XLXI_57/Q41<2>/XLXI_57/Q41<2>_CLKF__$INT = MA1 & MB1 & !MC1;

MACROCELL | 3 | 6 | XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT
ATTRIBUTES | 199424 | 0
OUTPUTMC | 4 | 3 | 12 | 3 | 11 | 3 | 10 | 3 | 9
INPUTS | 3 | MA0  | MB0  | MC0
INPUTP | 3 | 59 | 50 | 49
EQ | 1 | 
   XLXI_57/Q4<2>/XLXI_57/Q4<2>_CLKF__$INT = MA0 & MB0 & !MC0;

MACROCELL | 0 | 7 | _6_
ATTRIBUTES | 265984 | 0
INPUTS | 3 | CS  | A2  | D<7>_BUFR
INPUTMC | 1 | 2 | 14
INPUTP | 2 | 25 | 26
EQ | 2 | 
   D<7> = D<7>_BUFR;
   D<7>.OE = !CS & A2;

MACROCELL | 0 | 6 | _7_
ATTRIBUTES | 265984 | 0
INPUTS | 3 | CS  | A2  | D<6>_BUFR
INPUTMC | 1 | 3 | 13
INPUTP | 2 | 25 | 26
EQ | 2 | 
   D<6> = D<6>_BUFR;
   D<6>.OE = !CS & A2;

MACROCELL | 0 | 5 | _8_
ATTRIBUTES | 265984 | 0
INPUTS | 3 | CS  | A2  | D<5>_BUFR
INPUTMC | 1 | 2 | 15
INPUTP | 2 | 25 | 26
EQ | 2 | 
   D<5> = D<5>_BUFR;
   D<5>.OE = !CS & A2;

MACROCELL | 0 | 4 | _9_
ATTRIBUTES | 265984 | 0
INPUTS | 3 | CS  | A2  | D<4>_BUFR
INPUTMC | 1 | 3 | 14
INPUTP | 2 | 25 | 26
EQ | 2 | 
   D<4> = D<4>_BUFR;
   D<4>.OE = !CS & A2;

MACROCELL | 0 | 3 | _10_
ATTRIBUTES | 265984 | 0
INPUTS | 3 | CS  | A2  | D<3>_BUFR
INPUTMC | 1 | 3 | 15
INPUTP | 2 | 25 | 26
EQ | 2 | 
   D<3> = D<3>_BUFR;
   D<3>.OE = !CS & A2;

PIN | CS | 64 | 0 | N/A | 25 | 30 | 1 | 7 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | 0 | 3 | 0 | 4 | 0 | 5 | 0 | 6 | 0 | 7 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | A2 | 64 | 0 | N/A | 26 | 30 | 1 | 7 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | 0 | 3 | 0 | 4 | 0 | 5 | 0 | 6 | 0 | 7 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | A1 | 64 | 0 | N/A | 24 | 30 | 1 | 7 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | 3 | 15 | 3 | 14 | 2 | 15 | 3 | 13 | 2 | 14 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | A0 | 64 | 0 | N/A | 10 | 30 | 1 | 7 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 0 | 0 | 0 | 1 | 0 | 2 | 3 | 15 | 3 | 14 | 2 | 15 | 3 | 13 | 2 | 14 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | WR | 64 | 0 | N/A | 7 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | RESET | 64 | 0 | N/A | 91 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | MR_0<0> | 64 | 0 | N/A | 64 | 1 | 0 | 0
PIN | MR_2<0> | 64 | 0 | N/A | 33 | 2 | 0 | 0 | 0 | 16
PIN | MR_1<0> | 64 | 0 | N/A | 60 | 2 | 0 | 0 | 1 | 11
PIN | MR_1<1> | 64 | 0 | N/A | 58 | 2 | 0 | 1 | 1 | 11
PIN | MR_0<1> | 64 | 0 | N/A | 73 | 1 | 0 | 1
PIN | MR_2<1> | 64 | 0 | N/A | 48 | 2 | 0 | 1 | 0 | 16
PIN | MR_0<2> | 64 | 0 | N/A | 67 | 1 | 0 | 2
PIN | MR_2<2> | 64 | 0 | N/A | 47 | 2 | 0 | 2 | 0 | 16
PIN | MR_1<2> | 64 | 0 | N/A | 65 | 2 | 0 | 2 | 1 | 11
PIN | MR_0<3> | 64 | 0 | N/A | 74 | 1 | 3 | 15
PIN | MR_2<3> | 64 | 0 | N/A | 31 | 1 | 3 | 15
PIN | MR_1<3> | 64 | 0 | N/A | 66 | 1 | 3 | 15
PIN | MR_0<4> | 64 | 0 | N/A | 77 | 1 | 3 | 14
PIN | MR_2<4> | 64 | 0 | N/A | 44 | 1 | 3 | 14
PIN | MR_1<4> | 64 | 0 | N/A | 61 | 1 | 3 | 14
PIN | MR_0<5> | 64 | 0 | N/A | 71 | 1 | 2 | 15
PIN | MR_2<5> | 64 | 0 | N/A | 43 | 1 | 2 | 15
PIN | MR_1<5> | 64 | 0 | N/A | 69 | 1 | 2 | 15
PIN | MR_0<6> | 64 | 0 | N/A | 81 | 1 | 3 | 13
PIN | MR_2<6> | 64 | 0 | N/A | 29 | 1 | 3 | 13
PIN | MR_1<6> | 64 | 0 | N/A | 70 | 1 | 3 | 13
PIN | MR_0<7> | 64 | 0 | N/A | 78 | 1 | 2 | 14
PIN | MR_2<7> | 64 | 0 | N/A | 37 | 1 | 2 | 14
PIN | MR_1<7> | 64 | 0 | N/A | 62 | 1 | 2 | 14
PIN | MA1 | 64 | 0 | N/A | 57 | 5 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 1
PIN | MB1 | 64 | 0 | N/A | 55 | 5 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 1
PIN | MA0 | 64 | 0 | N/A | 59 | 5 | 3 | 12 | 3 | 11 | 3 | 10 | 3 | 9 | 3 | 6
PIN | MB0 | 64 | 0 | N/A | 50 | 5 | 3 | 12 | 3 | 11 | 3 | 10 | 3 | 9 | 3 | 6
PIN | MC0 | 64 | 0 | N/A | 49 | 1 | 3 | 6
PIN | MC1 | 64 | 0 | N/A | 46 | 1 | 2 | 1
PIN | RD | 64 | 0 | N/A | 21 | 8 | 2 | 7 | 2 | 6 | 3 | 8 | 3 | 7 | 2 | 5 | 2 | 4 | 2 | 3 | 2 | 2
PIN | CLK8 | 64 | 0 | N/A | 20 | 1 | 1 | 12
PIN | INT_L0 | 64 | 0 | N/A | 8 | 1 | 1 | 14
PIN | CS1 | 128 | 0 | N/A | 89
PIN | M1CLR | 128 | 0 | N/A | 85
PIN | M1PS | 128 | 0 | N/A | 79
PIN | M1SG | 128 | 0 | N/A | 83
PIN | M2CLR | 128 | 0 | N/A | 35
PIN | M2PS | 128 | 0 | N/A | 52
PIN | M2SG | 128 | 0 | N/A | 36
PIN | PC1ON | 128 | 0 | N/A | 88
PIN | PC2ON | 128 | 0 | N/A | 72
PIN | REL0 | 128 | 0 | N/A | 84
PIN | SEN0 | 128 | 0 | N/A | 82
PIN | SEN1 | 128 | 0 | N/A | 87
PIN | SEN2 | 128 | 0 | N/A | 32
PIN | SPD2A | 128 | 0 | N/A | 54
PIN | SPDA1 | 128 | 0 | N/A | 86
PIN | SPDB1 | 128 | 0 | N/A | 53
PIN | SPDB2 | 128 | 0 | N/A | 38
PIN | D<5> | 128 | 0 | N/A | 13
PIN | D<6> | 128 | 0 | N/A | 22
PIN | ALMR | 128 | 0 | N/A | 5
PIN | UART0 | 128 | 0 | N/A | 27
PIN | CLK | 128 | 0 | N/A | 6
PIN | INT0 | 128 | 0 | N/A | 9
PIN | D<0> | 64 | 0 | N/A | 14 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | D<1> | 64 | 0 | N/A | 11 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | D<2> | 64 | 0 | N/A | 16 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | D<3> | 64 | 0 | N/A | 17 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | D<4> | 64 | 0 | N/A | 12 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
PIN | D<7> | 64 | 0 | N/A | 15 | 21 | 1 | 3 | 1 | 0 | 1 | 2 | 0 | 15 | 2 | 16 | 0 | 17 | 1 | 5 | 3 | 17 | 1 | 17 | 3 | 16 | 1 | 4 | 0 | 12 | 2 | 9 | 1 | 1 | 2 | 17 | 2 | 8 | 1 | 16 | 1 | 15 | 1 | 10 | 1 | 13 | 1 | 9
12

top.mfd - 源码说明

本页面展示了「xilinx xc9572 cpld 实现的伺服电机控制器」中的 top.mfd 源码文件，采用 MFD 编程语言编写，共 788 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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