📄 top.vhf
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--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 6.3i
-- \ \ Application :
-- / / Filename : top.vhf
-- /___/ /\ Timestamp : 04/26/2006 09:26:37
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name: top
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity top is
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
CLK8 : in std_logic;
CS : in std_logic;
INT_L0 : in std_logic;
MA0 : in std_logic;
MA1 : in std_logic;
MB0 : in std_logic;
MB1 : in std_logic;
MC0 : in std_logic;
MC1 : in std_logic;
MR_0 : in std_logic_vector (7 downto 0);
MR_1 : in std_logic_vector (7 downto 0);
MR_2 : in std_logic_vector (7 downto 0);
RD : in std_logic;
RESET : in std_logic;
WR : in std_logic;
ALMR : out std_logic;
CLK : out std_logic;
CS1 : out std_logic;
INT0 : out std_logic;
M1CLR : out std_logic;
M1PS : out std_logic;
M1SG : out std_logic;
M2CLR : out std_logic;
M2PS : out std_logic;
M2SG : out std_logic;
PC1ON : out std_logic;
PC2ON : out std_logic;
REL0 : out std_logic;
SEN0 : out std_logic;
SEN1 : out std_logic;
SEN2 : out std_logic;
SPDA1 : out std_logic;
SPDB1 : out std_logic;
SPDB2 : out std_logic;
SPD2A : out std_logic;
UART0 : out std_logic;
D : inout std_logic_vector (7 downto 0));
end top;
architecture BEHAVIORAL of top is
signal CLR0 : std_logic;
signal CLR1 : std_logic;
signal CSA1 : std_logic;
signal CSA2 : std_logic;
signal CS_U : std_logic;
signal CS2 : std_logic;
signal CS3 : std_logic;
signal CS4 : std_logic;
signal NC3 : std_logic;
signal NC4 : std_logic;
signal NC23 : std_logic;
signal XLXN_8 : std_logic_vector (7 downto 0);
component dq024
port ( G : in std_logic;
REST : in std_logic;
WR : in std_logic;
D : in std_logic_vector (7 downto 0);
DQ0 : out std_logic;
DQ1 : out std_logic;
DQ2 : out std_logic;
DQ3 : out std_logic;
DQ4 : out std_logic;
DQ5 : out std_logic;
DQ6 : out std_logic;
DQ7 : out std_logic;
DQ8 : out std_logic;
DQ9 : out std_logic;
DQ10 : out std_logic;
DQ11 : out std_logic;
DQ12 : out std_logic;
DQ13 : out std_logic;
DQ14 : out std_logic;
DQ15 : out std_logic;
DQ16 : out std_logic;
DQ17 : out std_logic;
DQ18 : out std_logic;
DQ19 : out std_logic;
DQ20 : out std_logic;
DQ21 : out std_logic;
DQ22 : out std_logic;
DQ23 : out std_logic);
end component;
component logic
port ( M0UART : in std_logic;
UART0 : out std_logic;
M1UART : in std_logic;
M2UART : in std_logic;
ALM0 : in std_logic;
ALM1 : in std_logic;
ALM2 : in std_logic;
INT_L0 : in std_logic;
CLK8 : in std_logic;
Addr1 : in std_logic;
Addr2 : in std_logic;
CS_U : in std_logic;
ALM_R : out std_logic;
INT0 : out std_logic;
CLK : out std_logic);
end component;
component mdecode
port ( MA0 : in std_logic;
MB0 : in std_logic;
MC0 : in std_logic;
MA1 : in std_logic;
MB1 : in std_logic;
MC1 : in std_logic;
RD : in std_logic;
O : out std_logic_vector (7 downto 0);
CLR0 : in std_logic;
CLR1 : in std_logic);
end component;
component sel4_1
port ( MR_0 : in std_logic_vector (7 downto 0);
MR_1 : in std_logic_vector (7 downto 0);
MR_2 : in std_logic_vector (7 downto 0);
MR_3 : in std_logic_vector (7 downto 0);
A1 : in std_logic;
CS : in std_logic;
DO : out std_logic_vector (7 downto 0);
A0 : in std_logic);
end component;
component decode
port ( A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
E : in std_logic;
D0 : out std_logic;
D1 : out std_logic;
D2 : out std_logic;
D3 : out std_logic);
end component;
begin
XLXI_36 : dq024
port map (D(7 downto 0)=>D(7 downto 0),
G=>CS3,
REST=>RESET,
WR=>WR,
DQ0=>SEN0,
DQ1=>CSA1,
DQ2=>CSA2,
DQ3=>REL0,
DQ4=>CS_U,
DQ5=>CLR0,
DQ6=>CLR1,
DQ7=>NC3,
DQ8=>M1PS,
DQ9=>M1SG,
DQ10=>M1CLR,
DQ11=>SEN1,
DQ12=>PC1ON,
DQ13=>SPDA1,
DQ14=>SPDB1,
DQ15=>NC4,
DQ16=>M2PS,
DQ17=>M2SG,
DQ18=>M2CLR,
DQ19=>SEN2,
DQ20=>PC2ON,
DQ21=>SPD2A,
DQ22=>SPDB2,
DQ23=>NC23);
XLXI_45 : logic
port map (Addr1=>CSA1,
Addr2=>CSA2,
ALM0=>MR_1(0),
ALM1=>MR_1(1),
ALM2=>MR_1(2),
CLK8=>CLK8,
CS_U=>CS_U,
INT_L0=>INT_L0,
M0UART=>MR_2(0),
M1UART=>MR_2(1),
M2UART=>MR_2(2),
ALM_R=>ALMR,
CLK=>CLK,
INT0=>INT0,
UART0=>UART0);
XLXI_57 : mdecode
port map (CLR0=>CLR0,
CLR1=>CLR1,
MA0=>MA0,
MA1=>MA1,
MB0=>MB0,
MB1=>MB1,
MC0=>MC0,
MC1=>MC1,
RD=>RD,
O(7 downto 0)=>XLXN_8(7 downto 0));
XLXI_58 : sel4_1
port map (A0=>A0,
A1=>A1,
CS=>CS4,
MR_0(7 downto 0)=>MR_0(7 downto 0),
MR_1(7 downto 0)=>MR_1(7 downto 0),
MR_2(7 downto 0)=>MR_2(7 downto 0),
MR_3(7 downto 0)=>XLXN_8(7 downto 0),
DO(7 downto 0)=>D(7 downto 0));
XLXI_60 : decode
port map (A0=>A0,
A1=>A1,
A2=>A2,
E=>CS,
D0=>CS1,
D1=>CS2,
D2=>CS3,
D3=>CS4);
end BEHAVIORAL;
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