sel4_1.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

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-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_3892_6
-- /___/   /\     Timestamp : 04/06/2006 12:12:19
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: sel4_1
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity sel4_1 is
   port ( A0   : in    std_logic; 
          A1   : in    std_logic; 
          CS   : in    std_logic; 
          MR_0 : in    std_logic_vector (7 downto 0); 
          MR_1 : in    std_logic_vector (7 downto 0); 
          MR_2 : in    std_logic_vector (7 downto 0); 
          MR_3 : in    std_logic_vector (7 downto 0); 
          DO   : out   std_logic_vector (7 downto 0));
end sel4_1;

architecture BEHAVIORAL of sel4_1 is
signal adr:std_logic_vector(1 downto 0); 
begin
 adr<=A1&A0;
 process(CS,adr,MR_0,MR_1,MR_2,MR_3)
 begin
  if(CS='1') then
  DO<="ZZZZZZZZ";
  else
   case adr is 
		 when  "00"=> DO<=MR_0; 
	    when  "01"=> DO<=MR_1;
	    when  "10"=> DO<=MR_2;
	    when  "11"=> DO<=MR_3;
  		 when others=> DO<="ZZZZZZZZ";
   end case;
  end if;
 end process;
end BEHAVIORAL;

-- synopsys translate_off
configuration CFG_sel4_1 of  sel4_1 is
   for BEHAVIORAL
   end for;
end CFG_sel4_1;
-- synopsys translate_on