sel4_1.mfd

xilinx xc9572 cpld 实现的伺服电机控制器

MDF Database:  version 1.0
MDF_INFO | sel4_1 | XC9572-10-TQ100
MACROCELL | 2 | 2 | DO_0_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_3<0>  | A0  | MR_1<0>  | MR_0<0>  | MR_2<0>  | CS
INPUTP | 7 | 89 | 71 | 29 | 88 | 52 | 27 | 87
EQ | 5 | 
   DO<0> = A1 & MR_0<0> & A0
	# A1 & MR_1<0> & !A0
	# !A1 & MR_2<0> & A0
	# !A1 & MR_3<0> & !A0;
   DO<0>.OE = !CS;

MACROCELL | 3 | 2 | DO_1_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_0<1>  | A0  | MR_2<1>  | MR_1<1>  | MR_3<1>  | CS
INPUTP | 7 | 89 | 49 | 29 | 33 | 59 | 14 | 87
EQ | 5 | 
   DO<1> = A1 & MR_0<1> & A0
	# A1 & MR_1<1> & !A0
	# !A1 & MR_2<1> & A0
	# !A1 & MR_3<1> & !A0;
   DO<1>.OE = !CS;

MACROCELL | 1 | 2 | DO_2_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_2<2>  | A0  | MR_0<2>  | MR_1<2>  | MR_3<2>  | CS
INPUTP | 7 | 89 | 82 | 29 | 46 | 38 | 11 | 87
EQ | 5 | 
   DO<2> = A1 & MR_0<2> & A0
	# A1 & MR_1<2> & !A0
	# !A1 & MR_2<2> & A0
	# !A1 & MR_3<2> & !A0;
   DO<2>.OE = !CS;

MACROCELL | 2 | 9 | DO_3_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_1<3>  | A0  | MR_3<3>  | MR_0<3>  | MR_2<3>  | CS
INPUTP | 7 | 89 | 7 | 29 | 64 | 13 | 86 | 87
EQ | 5 | 
   DO<3> = A1 & MR_0<3> & A0
	# A1 & MR_1<3> & !A0
	# !A1 & MR_2<3> & A0
	# !A1 & MR_3<3> & !A0;
   DO<3>.OE = !CS;

MACROCELL | 3 | 9 | DO_4_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_1<4>  | A0  | MR_3<4>  | MR_0<4>  | MR_2<4>  | CS
INPUTP | 7 | 89 | 70 | 29 | 44 | 55 | 30 | 87
EQ | 5 | 
   DO<4> = A1 & MR_0<4> & A0
	# A1 & MR_1<4> & !A0
	# !A1 & MR_2<4> & A0
	# !A1 & MR_3<4> & !A0;
   DO<4>.OE = !CS;

MACROCELL | 0 | 2 | DO_5_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_3<5>  | A0  | MR_1<5>  | MR_0<5>  | MR_2<5>  | CS
INPUTP | 7 | 89 | 58 | 29 | 9 | 67 | 15 | 87
EQ | 5 | 
   DO<5> = A1 & MR_0<5> & A0
	# A1 & MR_1<5> & !A0
	# !A1 & MR_2<5> & A0
	# !A1 & MR_3<5> & !A0;
   DO<5>.OE = !CS;

MACROCELL | 0 | 9 | DO_6_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_1<6>  | A0  | MR_3<6>  | MR_0<6>  | MR_2<6>  | CS
INPUTP | 7 | 89 | 50 | 29 | 26 | 62 | 12 | 87
EQ | 5 | 
   DO<6> = MR_0<6> & A1 & A0
	# A1 & MR_1<6> & !A0
	# !A1 & MR_2<6> & A0
	# !A1 & MR_3<6> & !A0;
   DO<6>.OE = !CS;

MACROCELL | 1 | 11 | DO_7_OBUFE
ATTRIBUTES | 265984 | 0
INPUTS | 7 | A1  | MR_2<7>  | A0  | MR_0<7>  | MR_1<7>  | MR_3<7>  | CS
INPUTP | 7 | 89 | 81 | 29 | 61 | 31 | 10 | 87
EQ | 5 | 
   DO<7> = A1 & MR_0<7> & A0
	# A1 & MR_1<7> & !A0
	# !A1 & MR_2<7> & A0
	# !A1 & MR_3<7> & !A0;
   DO<7>.OE = !CS;

PIN | CS | 64 | 0 | N/A | 87 | 8 | 2 | 2 | 3 | 2 | 1 | 2 | 2 | 9 | 3 | 9 | 0 | 2 | 0 | 9 | 1 | 11
PIN | A1 | 64 | 0 | N/A | 89 | 8 | 2 | 2 | 3 | 2 | 1 | 2 | 2 | 9 | 3 | 9 | 0 | 2 | 0 | 9 | 1 | 11
PIN | A0 | 64 | 0 | N/A | 29 | 8 | 2 | 2 | 3 | 2 | 1 | 2 | 2 | 9 | 3 | 9 | 0 | 2 | 0 | 9 | 1 | 11
PIN | MR_3<0> | 64 | 0 | N/A | 71 | 1 | 2 | 2
PIN | MR_1<0> | 64 | 0 | N/A | 88 | 1 | 2 | 2
PIN | MR_0<0> | 64 | 0 | N/A | 52 | 1 | 2 | 2
PIN | MR_2<0> | 64 | 0 | N/A | 27 | 1 | 2 | 2
PIN | MR_0<1> | 64 | 0 | N/A | 49 | 1 | 3 | 2
PIN | MR_2<1> | 64 | 0 | N/A | 33 | 1 | 3 | 2
PIN | MR_1<1> | 64 | 0 | N/A | 59 | 1 | 3 | 2
PIN | MR_3<1> | 64 | 0 | N/A | 14 | 1 | 3 | 2
PIN | MR_2<2> | 64 | 0 | N/A | 82 | 1 | 1 | 2
PIN | MR_0<2> | 64 | 0 | N/A | 46 | 1 | 1 | 2
PIN | MR_1<2> | 64 | 0 | N/A | 38 | 1 | 1 | 2
PIN | MR_3<2> | 64 | 0 | N/A | 11 | 1 | 1 | 2
PIN | MR_1<3> | 64 | 0 | N/A | 7 | 1 | 2 | 9
PIN | MR_3<3> | 64 | 0 | N/A | 64 | 1 | 2 | 9
PIN | MR_0<3> | 64 | 0 | N/A | 13 | 1 | 2 | 9
PIN | MR_2<3> | 64 | 0 | N/A | 86 | 1 | 2 | 9
PIN | MR_1<4> | 64 | 0 | N/A | 70 | 1 | 3 | 9
PIN | MR_3<4> | 64 | 0 | N/A | 44 | 1 | 3 | 9
PIN | MR_0<4> | 64 | 0 | N/A | 55 | 1 | 3 | 9
PIN | MR_2<4> | 64 | 0 | N/A | 30 | 1 | 3 | 9
PIN | MR_3<5> | 64 | 0 | N/A | 58 | 1 | 0 | 2
PIN | MR_1<5> | 64 | 0 | N/A | 9 | 1 | 0 | 2
PIN | MR_0<5> | 64 | 0 | N/A | 67 | 1 | 0 | 2
PIN | MR_2<5> | 64 | 0 | N/A | 15 | 1 | 0 | 2
PIN | MR_1<6> | 64 | 0 | N/A | 50 | 1 | 0 | 9
PIN | MR_3<6> | 64 | 0 | N/A | 26 | 1 | 0 | 9
PIN | MR_0<6> | 64 | 0 | N/A | 62 | 1 | 0 | 9
PIN | MR_2<6> | 64 | 0 | N/A | 12 | 1 | 0 | 9
PIN | MR_2<7> | 64 | 0 | N/A | 81 | 1 | 1 | 11
PIN | MR_0<7> | 64 | 0 | N/A | 61 | 1 | 1 | 11
PIN | MR_1<7> | 64 | 0 | N/A | 31 | 1 | 1 | 11
PIN | MR_3<7> | 64 | 0 | N/A | 10 | 1 | 1 | 11
PIN | DO<0> | 128 | 0 | N/A | 43
PIN | DO<1> | 128 | 0 | N/A | 65
PIN | DO<2> | 128 | 0 | N/A | 83
PIN | DO<3> | 128 | 0 | N/A | 54
PIN | DO<4> | 128 | 0 | N/A | 73
PIN | DO<5> | 128 | 0 | N/A | 16
PIN | DO<6> | 128 | 0 | N/A | 25
PIN | DO<7> | 128 | 0 | N/A | 5