📄 mdecode.rpt
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*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 3/33
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 66 I/O
O<1> 2 0 0 3 FB4_2 STD 64 I/O O
(unused) 0 0 0 5 FB4_3 71 I/O
(unused) 0 0 0 5 FB4_4 72 I/O
(unused) 0 0 0 5 FB4_5 67 I/O
(unused) 0 0 0 5 FB4_6 76 I/O
(unused) 0 0 0 5 FB4_7 77 I/O
(unused) 0 0 0 5 FB4_8 68 I/O I
(unused) 0 0 0 5 FB4_9 70 I/O
O<6> 2 0 0 3 FB4_10 STD 81 I/O O
(unused) 0 0 0 5 FB4_11 74 I/O I
(unused) 0 0 0 5 FB4_12 82 I/O
(unused) 0 0 0 5 FB4_13 85 I/O
(unused) 0 0 0 5 FB4_14 78 I/O
(unused) 0 0 0 5 FB4_15 89 I/O
(unused) 0 0 0 5 FB4_16 86 I/O
(unused) 0 0 0 5 FB4_17 90 I/O
(unused) 0 0 0 5 FB4_18 79 I/O
Signals Used by Logic in Function Block
1: Q41<2> 2: Q4<1> 3: RD
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
O<1> .XX..................................... 2 2
O<6> X.X..................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
FDCPE_O0: FDCPE port map (O(0),'0','0',O_CLR(0),O_PRE(0));
O_CLR(0) <= (NOT Q4(0) AND NOT RD);
O_PRE(0) <= (Q4(0) AND NOT RD);
FDCPE_O1: FDCPE port map (O(1),'0','0',O_CLR(1),O_PRE(1));
O_CLR(1) <= (NOT Q4(1) AND NOT RD);
O_PRE(1) <= (Q4(1) AND NOT RD);
FDCPE_O2: FDCPE port map (O(2),'0','0',O_CLR(2),O_PRE(2));
O_CLR(2) <= (NOT Q4(2) AND NOT RD);
O_PRE(2) <= (Q4(2) AND NOT RD);
FDCPE_O3: FDCPE port map (O(3),'0','0',O_CLR(3),O_PRE(3));
O_CLR(3) <= (NOT Q4(3) AND NOT RD);
O_PRE(3) <= (Q4(3) AND NOT RD);
FDCPE_O4: FDCPE port map (O(4),'0','0',O_CLR(4),O_PRE(4));
O_CLR(4) <= (NOT Q41(0) AND NOT RD);
O_PRE(4) <= (Q41(0) AND NOT RD);
FDCPE_O5: FDCPE port map (O(5),'0','0',O_CLR(5),O_PRE(5));
O_CLR(5) <= (NOT RD AND NOT Q41(1).FBK.LFBK);
O_PRE(5) <= (NOT RD AND Q41(1).FBK.LFBK);
FDCPE_O6: FDCPE port map (O(6),'0','0',O_CLR(6),O_PRE(6));
O_CLR(6) <= (NOT Q41(2) AND NOT RD);
O_PRE(6) <= (Q41(2) AND NOT RD);
FDCPE_O7: FDCPE port map (O(7),'0','0',O_CLR(7),O_PRE(7));
O_CLR(7) <= (NOT RD AND NOT Q41(3).FBK.LFBK);
O_PRE(7) <= (NOT RD AND Q41(3).FBK.LFBK);
FTCPE_Q410: FTCPE port map (Q41(0),Q41_T(0),NOT Q41(2)/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
Q41_T(0) <= ((MA1 AND NOT MB1)
OR (NOT MA1 AND MB1));
FTCPE_Q411: FTCPE port map (Q41(1),Q41_T(1),NOT Q41(2)/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
Q41_T(1) <= ((MA1 AND NOT MB1 AND Q41(0).FBK.LFBK)
OR (NOT MA1 AND MB1 AND NOT Q41(0).FBK.LFBK));
FTCPE_Q412: FTCPE port map (Q41(2),Q41_T(2),NOT Q41(2)/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
Q41_T(2) <= ((MA1 AND NOT MB1 AND Q41(0).FBK.LFBK AND Q41(1).FBK.LFBK)
OR (NOT MA1 AND MB1 AND NOT Q41(0).FBK.LFBK AND NOT Q41(1).FBK.LFBK));
Q41(2)/Q41(2)_CLKF__$INT <= (MA1 AND MB1 AND NOT MC1);
FTCPE_Q413: FTCPE port map (Q41(3),Q41_T(3),NOT Q41(2)/Q41(2)_CLKF__$INT.FBK.LFBK,CLR1,'0');
Q41_T(3) <= ((MA1 AND NOT MB1 AND Q41(3).FBK.LFBK)
OR (NOT MA1 AND MB1 AND NOT Q41(3).FBK.LFBK));
FTCPE_Q40: FTCPE port map (Q4(0),Q4_T(0),NOT Q4(2)/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
Q4_T(0) <= ((MA0 AND NOT MB0)
OR (NOT MA0 AND MB0));
FTCPE_Q41: FTCPE port map (Q4(1),Q4_T(1),NOT Q4(2)/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
Q4_T(1) <= ((MA0 AND NOT MB0 AND Q4(0).FBK.LFBK)
OR (NOT MA0 AND MB0 AND NOT Q4(0).FBK.LFBK));
FTCPE_Q42: FTCPE port map (Q4(2),Q4_T(2),NOT Q4(2)/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
Q4_T(2) <= ((MA0 AND NOT MB0 AND Q4(0).FBK.LFBK AND Q4(1).FBK.LFBK)
OR (NOT MA0 AND MB0 AND NOT Q4(0).FBK.LFBK AND NOT Q4(1).FBK.LFBK));
Q4(2)/Q4(2)_CLKF__$INT <= (MA0 AND MB0 AND NOT MC0);
FTCPE_Q43: FTCPE port map (Q4(3),Q4_T(3),NOT Q4(2)/Q4(2)_CLKF__$INT.FBK.LFBK,CLR0,'0');
Q4_T(3) <= ((MA0 AND NOT MB0 AND Q4(3).FBK.LFBK)
OR (NOT MA0 AND MB0 AND NOT Q4(3).FBK.LFBK));
Register Legend:
FDCPE (Q,D,C,CLR,PRE);
FTCPE (Q,D,C,CLR,PRE);
LDCP (Q,D,G,CLR,PRE);
**************************** Device Pin Out ****************************
Device : XC9572-10-TQ100
--------------------------------------------------
/100 98 96 94 92 90 88 86 84 82 80 78 76 \
| 99 97 95 93 91 89 87 85 83 81 79 77 |
| 1 75 |
| 2 74 |
| 3 73 |
| 4 72 |
| 5 71 |
| 6 70 |
| 7 69 |
| 8 68 |
| 9 67 |
| 10 66 |
| 11 65 |
| 12 64 |
| 13 XC9572-10-TQ100 63 |
| 14 62 |
| 15 61 |
| 16 60 |
| 17 59 |
| 18 58 |
| 19 57 |
| 20 56 |
| 21 55 |
| 22 54 |
| 23 53 |
| 24 52 |
| 25 51 |
| 27 29 31 33 35 37 39 41 43 45 47 49 |
\26 28 30 32 34 36 38 40 42 44 46 48 50 /
--------------------------------------------------
Pin Signal Pin Signal
No. Name No. Name
1 TIE 51 VCC
2 NC 52 TIE
3 TIE 53 TIE
4 TIE 54 TIE
5 VCC 55 TIE
6 O<3> 56 MB1
7 NC 57 VCC
8 TIE 58 TIE
9 TIE 59 TIE
10 TIE 60 O<4>
11 MA0 61 TIE
12 TIE 62 GND
13 O<5> 63 TIE
14 CLR1 64 O<1>
15 TIE 65 TIE
16 TIE 66 TIE
17 MC0 67 TIE
18 TIE 68 CLR0
19 NC 69 GND
20 TIE 70 TIE
21 GND 71 TIE
22 TIE 72 TIE
23 TIE 73 NC
24 NC 74 MB0
25 TIE 75 GND
26 VCC 76 TIE
27 TIE 77 TIE
28 O<7> 78 TIE
29 MC1 79 TIE
30 TIE 80 NC
31 GND 81 O<6>
32 O<0> 82 TIE
33 TIE 83 TDO
34 NC 84 GND
35 TIE 85 TIE
36 TIE 86 TIE
37 TIE 87 TIE
38 VCC 88 VCC
39 TIE 89 TIE
40 TIE 90 TIE
41 TIE 91 TIE
42 TIE 92 TIE
43 NC 93 TIE
44 GND 94 O<2>
45 TDI 95 MA1
46 NC 96 TIE
47 TMS 97 RD
48 TCK 98 VCC
49 TIE 99 TIE
50 TIE 100 GND
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xc9572-10-TQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Slew Rate : SLOW
Power Mode : AUTO
Ground on Unused IOs : OFF
Global Clock Optimization : OFF
Global Set/Reset Optimization : OFF
Global Ouput Enable Optimization : OFF
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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