📄 mdecode.rpt
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cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: mdecode Date: 4-26-2006, 9:23AM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
18 /72 ( 25%) 50 /360 ( 14%) 16 /72 ( 22%) 17 /72 ( 24%) 26 /144 ( 18%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 9 9 | I/O : 17 49
Output : 8 8 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 17 17
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 16
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 18 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 18 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
O<0> 2 2 FB3_2 STD SLOW 32 I/O O RESET
O<1> 2 2 FB4_2 STD SLOW 64 I/O O RESET
O<2> 2 2 FB2_2 STD SLOW 94 I/O O RESET
O<3> 2 2 FB2_12 STD SLOW 6 I/O O RESET
O<4> 2 2 FB3_10 STD SLOW 60 I/O O RESET
O<5> 2 2 FB1_2 STD SLOW 13 I/O O RESET
O<6> 2 2 FB4_10 STD SLOW 81 I/O O RESET
O<7> 2 2 FB1_10 STD SLOW 28 I/O O RESET
Q41<0> 4 4 FB1_18 STD 40 I/O (b) RESET
Q41<1> 4 5 FB1_17 STD 30 I/O (b) RESET
Q41<2> 4 6 FB1_16 STD 39 I/O (b) RESET
Q41<2>/Q41<2>_CLKF__$INT 1 3 FB1_9 STD 22 GCK/I/O (b)
Q41<3> 4 5 FB1_15 STD 29 I/O I RESET
Q4<0> 4 4 FB1_14 STD 27 GCK/I/O (b) RESET
Q4<1> 4 5 FB1_13 STD 36 I/O (b) RESET
Q4<2> 4 6 FB1_12 STD 33 I/O (b) RESET
Q4<2>/Q4<2>_CLKF__$INT 1 3 FB1_8 STD 17 I/O I
Q4<3> 4 5 FB1_11 STD 23 GCK/I/O (b) RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
CLR0 FB4_8 68 I/O I
CLR1 FB1_5 14 I/O I
MA0 FB2_15 11 I/O I
MA1 FB2_5 95 I/O I
MB0 FB4_11 74 I/O I
MB1 FB3_15 56 I/O I
MC0 FB1_8 17 I/O I
MC1 FB1_15 29 I/O I
RD FB2_8 97 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 12 17 17 38 2/0 18
FB2 2 3 3 4 2/0 18
FB3 2 3 3 4 2/0 18
FB4 2 3 3 4 2/0 18
---- ----- ----- -----
18 50 8/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 17/19
Number of signals used by logic mapping into function block: 17
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 16 I/O
O<5> 2 0 0 3 FB1_2 STD 13 I/O O
(unused) 0 0 0 5 FB1_3 18 I/O
(unused) 0 0 0 5 FB1_4 20 I/O
(unused) 0 0 0 5 FB1_5 14 I/O I
(unused) 0 0 0 5 FB1_6 15 I/O
(unused) 0 0 0 5 FB1_7 25 I/O
Q4<2>/Q4<2>_CLKF__$INT
1 0 0 4 FB1_8 STD 17 I/O I
Q41<2>/Q41<2>_CLKF__$INT
1 0 0 4 FB1_9 STD 22 GCK/I/O (b)
O<7> 2 0 0 3 FB1_10 STD 28 I/O O
Q4<3> 4 0 0 1 FB1_11 STD 23 GCK/I/O (b)
Q4<2> 4 0 0 1 FB1_12 STD 33 I/O (b)
Q4<1> 4 0 0 1 FB1_13 STD 36 I/O (b)
Q4<0> 4 0 0 1 FB1_14 STD 27 GCK/I/O (b)
Q41<3> 4 0 0 1 FB1_15 STD 29 I/O I
Q41<2> 4 0 0 1 FB1_16 STD 39 I/O (b)
Q41<1> 4 0 0 1 FB1_17 STD 30 I/O (b)
Q41<0> 4 0 0 1 FB1_18 STD 40 I/O (b)
Signals Used by Logic in Function Block
1: CLR0 7: MC0 13: Q4<0>.FBK.LFBK
2: CLR1 8: MC1 14: Q4<1>.FBK.LFBK
3: MA0 9: Q41<0>.FBK.LFBK 15: Q4<2>/Q4<2>_CLKF__$INT.FBK.LFBK
4: MA1 10: Q41<1>.FBK.LFBK 16: Q4<3>.FBK.LFBK
5: MB0 11: Q41<2>/Q41<2>_CLKF__$INT.FBK.LFBK
17: RD
6: MB1 12: Q41<3>.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
O<5> .........X......X....................... 2 2
Q4<2>/Q4<2>_CLKF__$INT
..X.X.X................................. 3 3
Q41<2>/Q41<2>_CLKF__$INT
...X.X.X................................ 3 3
O<7> ...........X....X....................... 2 2
Q4<3> X.X.X.........XX........................ 5 5
Q4<2> X.X.X.......XXX......................... 6 6
Q4<1> X.X.X.......X.X......................... 5 5
Q4<0> X.X.X.........X......................... 4 4
Q41<3> .X.X.X....XX............................ 5 5
Q41<2> .X.X.X..XXX............................. 6 6
Q41<1> .X.X.X..X.X............................. 5 5
Q41<0> .X.X.X....X............................. 4 4
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 3/33
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
O<2> 2 0 0 3 FB2_2 STD 94 I/O O
(unused) 0 0 0 5 FB2_3 91 I/O
(unused) 0 0 0 5 FB2_4 93 I/O
(unused) 0 0 0 5 FB2_5 95 I/O I
(unused) 0 0 0 5 FB2_6 96 I/O
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
(unused) 0 0 0 5 FB2_8 97 I/O I
(unused) 0 0 0 5 FB2_9 99 GSR/I/O
(unused) 0 0 0 5 FB2_10 1 I/O
(unused) 0 0 0 5 FB2_11 4 GTS/I/O
O<3> 2 0 0 3 FB2_12 STD 6 I/O O
(unused) 0 0 0 5 FB2_13 8 I/O
(unused) 0 0 0 5 FB2_14 9 I/O
(unused) 0 0 0 5 FB2_15 11 I/O I
(unused) 0 0 0 5 FB2_16 10 I/O
(unused) 0 0 0 5 FB2_17 12 I/O
(unused) 0 0 0 5 FB2_18 92 I/O
Signals Used by Logic in Function Block
1: Q4<2> 2: Q4<3> 3: RD
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
O<2> X.X..................................... 2 2
O<3> .XX..................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 3/33
Number of signals used by logic mapping into function block: 3
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 41 I/O
O<0> 2 0 0 3 FB3_2 STD 32 I/O O
(unused) 0 0 0 5 FB3_3 49 I/O
(unused) 0 0 0 5 FB3_4 50 I/O
(unused) 0 0 0 5 FB3_5 35 I/O
(unused) 0 0 0 5 FB3_6 53 I/O
(unused) 0 0 0 5 FB3_7 54 I/O
(unused) 0 0 0 5 FB3_8 37 I/O
(unused) 0 0 0 5 FB3_9 42 I/O
O<4> 2 0 0 3 FB3_10 STD 60 I/O O
(unused) 0 0 0 5 FB3_11 52 I/O
(unused) 0 0 0 5 FB3_12 61 I/O
(unused) 0 0 0 5 FB3_13 63 I/O
(unused) 0 0 0 5 FB3_14 55 I/O
(unused) 0 0 0 5 FB3_15 56 I/O I
(unused) 0 0 0 5 FB3_16 65 I/O
(unused) 0 0 0 5 FB3_17 58 I/O
(unused) 0 0 0 5 FB3_18 59 I/O
Signals Used by Logic in Function Block
1: Q41<0> 2: Q4<0> 3: RD
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
O<0> .XX..................................... 2 2
O<4> X.X..................................... 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
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