📄 counter8.mfd

📁 xilinx xc9572 cpld 实现的伺服电机控制器
💻 MFD
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INPUTS | 3 | Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D  | Qout<5>
INPUTMC | 3 | 2 | 14 | 2 | 16 | 3 | 7
EQ | 5 | 
   Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2 = Qout<5> & 
	!Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D;

MACROCELL | 2 | 14 | Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 3 | 7 | 2 | 13 | 3 | 6
INPUTS | 3 | Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D  | Qout<4>
INPUTMC | 3 | 1 | 6 | 2 | 17 | 2 | 12
EQ | 5 | 
   Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2 = Qout<4> & 
	!Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D;

MACROCELL | 1 | 6 | Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 2 | 12 | 2 | 14 | 2 | 11 | 1 | 7
INPUTS | 7 | Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D  | Qout<3>  | CE  | L  | Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
INPUTMC | 5 | 1 | 8 | 1 | 14 | 3 | 2 | 1 | 5 | 1 | 11
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 1 | 7
EQ | 8 | 
   Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2 = Qout<3> & 
	!Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D;
    Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D

MACROCELL | 1 | 8 | Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 3 | 2 | 1 | 6 | 3 | 1
INPUTS | 3 | Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D  | Qout<2>
INPUTMC | 3 | 1 | 9 | 1 | 15 | 2 | 7
EQ | 5 | 
   Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2 = Qout<2> & 
	!Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D;

MACROCELL | 1 | 9 | Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 2 | 7 | 1 | 8 | 2 | 6
INPUTS | 3 | UP  | Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D  | Qout<0>
INPUTMC | 2 | 1 | 16 | 0 | 15
INPUTP | 1 | 9
EQ | 4 | 
   Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2 = Qout<0> & 
	Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
	# !UP & 
	!Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D;

MACROCELL | 1 | 16 | Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 0 | 11 | 1 | 9 | 0 | 10
INPUTS | 2 | UP  | Qout<1>
INPUTMC | 1 | 0 | 11
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D = UP
	$ Qout<1>;

MACROCELL | 1 | 15 | Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 2 | 7 | 1 | 8 | 2 | 6
INPUTS | 2 | UP  | Qout<2>
INPUTMC | 1 | 2 | 7
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D = UP
	$ Qout<2>;

MACROCELL | 1 | 14 | Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 3 | 2 | 1 | 6 | 3 | 1
INPUTS | 2 | UP  | Qout<3>
INPUTMC | 1 | 3 | 2
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D = UP
	$ Qout<3>;

MACROCELL | 2 | 17 | Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 2 | 12 | 2 | 14 | 2 | 11
INPUTS | 2 | UP  | Qout<4>
INPUTMC | 1 | 2 | 12
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D = UP
	$ Qout<4>;

MACROCELL | 2 | 16 | Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 3 | 7 | 2 | 13 | 3 | 6
INPUTS | 2 | UP  | Qout<5>
INPUTMC | 1 | 3 | 7
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D = UP
	$ Qout<5>;

MACROCELL | 2 | 15 | Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 3 | 12 | 2 | 11 | 3 | 11
INPUTS | 2 | UP  | Qout<6>
INPUTMC | 1 | 3 | 12
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D = UP
	$ Qout<6>;

MACROCELL | 1 | 12 | Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 1 | 2 | 1 | 5 | 1 | 1 | 1 | 13
INPUTS | 6 | UP  | Qout<7>  | CE  | L  | Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
INPUTMC | 3 | 1 | 2 | 1 | 4 | 1 | 10
INPUTP | 3 | 9 | 67 | 58
EXPORTS | 1 | 1 | 13
EQ | 5 | 
   !Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D = UP
	$ Qout<7>;
    Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D

MACROCELL | 1 | 11 | Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 1 | 7 | 1 | 4 | 1 | 6
INPUTS | 2 | UP  | Qout<8>
INPUTMC | 1 | 1 | 7
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D = UP
	$ Qout<8>;

MACROCELL | 1 | 10 | Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 1 | 13 | 1 | 3 | 1 | 12
INPUTS | 2 | UP  | Qout<9>
INPUTMC | 1 | 1 | 13
INPUTP | 1 | 9
EQ | 2 | 
   !Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D = UP
	$ Qout<9>;

MACROCELL | 1 | 17 | Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 0 | 2 | 0 | 7
INPUTS | 3 | UP  | Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2  | Qout<10>
INPUTMC | 2 | 1 | 3 | 2 | 2
INPUTP | 1 | 9
EQ | 5 | 
   Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2 = Qout<10> & !UP
	# Qout<10> & 
	Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
	# !UP & 
	Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2;

MACROCELL | 0 | 1 | EXP0_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 2
INPUTS | 3 | Qout<11>  | L  | Din<11>
INPUTMC | 1 | 0 | 2
INPUTP | 2 | 58 | 29
EXPORTS | 1 | 0 | 2
EQ | 1 | 
       EXP0_.EXP  =  Qout<11> & L & !Din<11>

MACROCELL | 0 | 6 | EXP1_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 7
INPUTS | 3 | Qout<12>  | L  | Din<12>
INPUTMC | 1 | 0 | 7
INPUTP | 2 | 58 | 26
EXPORTS | 1 | 0 | 7
EQ | 1 | 
       EXP1_.EXP  =  Qout<12> & L & !Din<12>

MACROCELL | 0 | 10 | EXP2_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 0 | 11
INPUTS | 4 | Qout<0>  | CE  | L  | Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
INPUTMC | 2 | 0 | 15 | 1 | 16
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 0 | 11
EQ | 2 | 
       EXP2_.EXP  =  Qout<0> & !CE & !L & 
	!Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D

MACROCELL | 1 | 1 | EXP3_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 1 | 2
INPUTS | 4 | CE  | L  | Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
INPUTMC | 2 | 2 | 11 | 1 | 12
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 1 | 2
EQ | 3 | 
       EXP3_.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D

MACROCELL | 2 | 1 | EXP4_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 2
INPUTS | 3 | Qout<10>  | L  | Din<10>
INPUTMC | 1 | 2 | 2
INPUTP | 2 | 58 | 81
EXPORTS | 1 | 2 | 2
EQ | 1 | 
       EXP4_.EXP  =  Qout<10> & L & !Din<10>

MACROCELL | 2 | 6 | EXP5_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 2 | 7
INPUTS | 4 | CE  | L  | Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
INPUTMC | 2 | 1 | 9 | 1 | 15
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 2 | 7
EQ | 3 | 
       EXP5_.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D

MACROCELL | 3 | 1 | EXP6_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 2
INPUTS | 4 | CE  | L  | Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
INPUTMC | 2 | 1 | 8 | 1 | 14
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 3 | 2
EQ | 3 | 
       EXP6_.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D

MACROCELL | 3 | 6 | EXP7_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 7
INPUTS | 4 | CE  | L  | Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
INPUTMC | 2 | 2 | 14 | 2 | 16
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 3 | 7
EQ | 3 | 
       EXP7_.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D

MACROCELL | 3 | 11 | EXP8_
ATTRIBUTES | 2048 | 0
OUTPUTMC | 1 | 3 | 12
INPUTS | 4 | CE  | L  | Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
INPUTMC | 2 | 2 | 13 | 2 | 15
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 3 | 12
EQ | 3 | 
       EXP8_.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D

PIN | CCLK | 64 | 0 | N/A | 87 | 13 | 0 | 15 | 2 | 2 | 0 | 2 | 0 | 11 | 2 | 7 | 3 | 2 | 2 | 12 | 3 | 7 | 3 | 12 | 1 | 2 | 1 | 7 | 1 | 13 | 0 | 7
PIN | CLR | 64 | 0 | N/A | 50 | 13 | 0 | 15 | 2 | 2 | 0 | 2 | 0 | 11 | 2 | 7 | 3 | 2 | 2 | 12 | 3 | 7 | 3 | 12 | 1 | 2 | 1 | 7 | 1 | 13 | 0 | 7
PIN | L | 64 | 0 | N/A | 58 | 25 | 0 | 15 | 2 | 2 | 0 | 2 | 0 | 11 | 2 | 7 | 3 | 2 | 2 | 12 | 3 | 7 | 3 | 12 | 1 | 2 | 1 | 7 | 1 | 13 | 0 | 7 | 0 | 1 | 0 | 6 | 0 | 10 | 1 | 1 | 1 | 6 | 1 | 12 | 2 | 1 | 2 | 6 | 2 | 11 | 3 | 1 | 3 | 6 | 3 | 11
PIN | Din<0> | 64 | 0 | N/A | 82 | 1 | 0 | 15
PIN | CE | 64 | 0 | N/A | 67 | 22 | 0 | 15 | 2 | 2 | 0 | 2 | 0 | 11 | 2 | 7 | 3 | 2 | 2 | 12 | 3 | 7 | 3 | 12 | 1 | 2 | 1 | 7 | 1 | 13 | 0 | 7 | 0 | 10 | 1 | 1 | 1 | 6 | 1 | 12 | 2 | 6 | 2 | 11 | 3 | 1 | 3 | 6 | 3 | 11
PIN | UP | 64 | 0 | N/A | 9 | 14 | 2 | 2 | 0 | 2 | 0 | 7 | 1 | 9 | 1 | 16 | 1 | 15 | 1 | 14 | 2 | 17 | 2 | 16 | 2 | 15 | 1 | 12 | 1 | 11 | 1 | 10 | 1 | 17
PIN | Din<10> | 64 | 0 | N/A | 81 | 2 | 2 | 2 | 2 | 1
PIN | Din<11> | 64 | 0 | N/A | 29 | 2 | 0 | 2 | 0 | 1
PIN | Din<1> | 64 | 0 | N/A | 12 | 1 | 0 | 11
PIN | Din<2> | 64 | 0 | N/A | 25 | 1 | 2 | 7
PIN | Din<3> | 64 | 0 | N/A | 31 | 1 | 3 | 2
PIN | Din<4> | 64 | 0 | N/A | 61 | 1 | 2 | 12
PIN | Din<5> | 64 | 0 | N/A | 10 | 1 | 3 | 7
PIN | Din<6> | 64 | 0 | N/A | 71 | 1 | 3 | 12
PIN | Din<7> | 64 | 0 | N/A | 46 | 1 | 1 | 2
PIN | Din<8> | 64 | 0 | N/A | 38 | 1 | 1 | 7
PIN | Din<9> | 64 | 0 | N/A | 11 | 1 | 1 | 13
PIN | Din<12> | 64 | 0 | N/A | 26 | 2 | 0 | 7 | 0 | 6
PIN | Qout<0> | 128 | 0 | N/A | 35
PIN | Qout<10> | 128 | 0 | N/A | 43
PIN | Qout<11> | 128 | 0 | N/A | 16
PIN | Qout<1> | 128 | 0 | N/A | 30
PIN | Qout<2> | 128 | 0 | N/A | 33
PIN | Qout<3> | 128 | 0 | N/A | 65
PIN | Qout<4> | 128 | 0 | N/A | 57
PIN | Qout<5> | 128 | 0 | N/A | 62
PIN | Qout<6> | 128 | 0 | N/A | 77
PIN | Qout<7> | 128 | 0 | N/A | 83
PIN | Qout<8> | 128 | 0 | N/A | 89
PIN | Qout<9> | 128 | 0 | N/A | 7
PIN | Qout<12> | 128 | 0 | N/A | 15
上一页 12
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