counter8.mfd

xilinx xc9572 cpld 实现的伺服电机控制器

MDF Database:  version 1.0
MDF_INFO | counter8 | XC9572-10-TQ100
MACROCELL | 0 | 15 | Temp<0>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 4 | 0 | 15 | 0 | 11 | 1 | 9 | 0 | 10
INPUTS | 6 | L  | Din<0>  | Qout<0>  | CE  | CCLK  | CLR
INPUTMC | 1 | 0 | 15
INPUTP | 5 | 58 | 82 | 67 | 87 | 50
EQ | 5 | 
   Qout<0>.D = L & Din<0>
	# Qout<0> & CE & !L
	# !Qout<0> & !CE & !L;
   Qout<0>.CLK = CCLK;
   Qout<0>.AR = CLR;

MACROCELL | 2 | 2 | Temp<10>
ATTRIBUTES | 4588336 | 0
OUTPUTMC | 3 | 2 | 2 | 1 | 17 | 2 | 1
INPUTS | 9 | UP  | CE  | L  | Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2  | Qout<10>  | Din<10>  | CCLK  | CLR  | EXP4_.EXP
INPUTMC | 3 | 1 | 3 | 2 | 2 | 2 | 1
INPUTP | 6 | 9 | 67 | 58 | 81 | 87 | 50
IMPORTS | 1 | 2 | 1
EQ | 9 | 
   Qout<10>.T = !Qout<10> & L & Din<10>
	# UP & !CE & !L & 
	Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
	# !UP & !CE & !L & 
	!Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
;Imported pterms FB3_2
	# Qout<10> & L & !Din<10>;
   Qout<10>.CLK = CCLK;
   Qout<10>.AR = CLR;

MACROCELL | 0 | 2 | Temp<11>
ATTRIBUTES | 4588336 | 0
OUTPUTMC | 3 | 0 | 2 | 0 | 7 | 0 | 1
INPUTS | 9 | UP  | CE  | L  | Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2  | Qout<11>  | Din<11>  | CCLK  | CLR  | EXP0_.EXP
INPUTMC | 3 | 1 | 17 | 0 | 2 | 0 | 1
INPUTP | 6 | 9 | 67 | 58 | 29 | 87 | 50
IMPORTS | 1 | 0 | 1
EQ | 9 | 
   Qout<11>.T = !Qout<11> & L & Din<11>
	# UP & !CE & !L & 
	Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
	# !UP & !CE & !L & 
	!Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
;Imported pterms FB1_2
	# Qout<11> & L & !Din<11>;
   Qout<11>.CLK = CCLK;
   Qout<11>.AR = CLR;

MACROCELL | 0 | 11 | Temp<1>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 2 | 0 | 11 | 1 | 16
INPUTS | 9 | L  | Din<1>  | Qout<1>  | CE  | Qout<0>  | Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D  | CCLK  | CLR  | EXP2_.EXP
INPUTMC | 4 | 0 | 11 | 0 | 15 | 1 | 16 | 0 | 10
INPUTP | 5 | 58 | 12 | 67 | 87 | 50
IMPORTS | 1 | 0 | 10
EQ | 9 | 
   Qout<1>.D = L & Din<1>
	# Qout<1> & CE & !L
	# !Qout<0> & !CE & !L & 
	Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D
;Imported pterms FB1_11
	# Qout<0> & !CE & !L & 
	!Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<1>__n0002<0>_D;
   Qout<1>.CLK = CCLK;
   Qout<1>.AR = CLR;

MACROCELL | 2 | 7 | Temp<2>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 2 | 7 | 1 | 8 | 1 | 15
INPUTS | 9 | L  | Din<2>  | Qout<2>  | CE  | Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D  | CCLK  | CLR  | EXP5_.EXP
INPUTMC | 4 | 2 | 7 | 1 | 9 | 1 | 15 | 2 | 6
INPUTP | 5 | 58 | 25 | 67 | 87 | 50
IMPORTS | 1 | 2 | 6
EQ | 11 | 
   Qout<2>.D = L & Din<2>
	# Qout<2> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D
;Imported pterms FB3_7
	# !CE & !L & 
	Temp_Maddsub__n0000__n0049<0>/Temp_Maddsub__n0000__n0049<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<2>__n0002<0>_D;
   Qout<2>.CLK = CCLK;
   Qout<2>.AR = CLR;

MACROCELL | 3 | 2 | Temp<3>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 3 | 2 | 1 | 6 | 1 | 14
INPUTS | 9 | L  | Din<3>  | Qout<3>  | CE  | Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D  | CCLK  | CLR  | EXP6_.EXP
INPUTMC | 4 | 3 | 2 | 1 | 8 | 1 | 14 | 3 | 1
INPUTP | 5 | 58 | 31 | 67 | 87 | 50
IMPORTS | 1 | 3 | 1
EQ | 11 | 
   Qout<3>.D = L & Din<3>
	# Qout<3> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D
;Imported pterms FB4_2
	# !CE & !L & 
	Temp_Maddsub__n0000__n0051<0>/Temp_Maddsub__n0000__n0051<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<3>__n0002<0>_D;
   Qout<3>.CLK = CCLK;
   Qout<3>.AR = CLR;

MACROCELL | 2 | 12 | Temp<4>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 2 | 12 | 2 | 14 | 2 | 17
INPUTS | 9 | L  | Din<4>  | Qout<4>  | CE  | Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D  | CCLK  | CLR  | Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2.EXP
INPUTMC | 4 | 2 | 12 | 1 | 6 | 2 | 17 | 2 | 11
INPUTP | 5 | 58 | 61 | 67 | 87 | 50
IMPORTS | 1 | 2 | 11
EQ | 11 | 
   Qout<4>.D = L & Din<4>
	# Qout<4> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
;Imported pterms FB3_12
	# !CE & !L & 
	Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D;
   Qout<4>.CLK = CCLK;
   Qout<4>.AR = CLR;

MACROCELL | 3 | 7 | Temp<5>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 3 | 7 | 2 | 13 | 2 | 16
INPUTS | 9 | L  | Din<5>  | Qout<5>  | CE  | Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D  | CCLK  | CLR  | EXP7_.EXP
INPUTMC | 4 | 3 | 7 | 2 | 14 | 2 | 16 | 3 | 6
INPUTP | 5 | 58 | 10 | 67 | 87 | 50
IMPORTS | 1 | 3 | 6
EQ | 11 | 
   Qout<5>.D = L & Din<5>
	# Qout<5> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D
;Imported pterms FB4_7
	# !CE & !L & 
	Temp_Maddsub__n0000__n0055<0>/Temp_Maddsub__n0000__n0055<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<5>__n0002<0>_D;
   Qout<5>.CLK = CCLK;
   Qout<5>.AR = CLR;

MACROCELL | 3 | 12 | Temp<6>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 3 | 12 | 2 | 11 | 2 | 15
INPUTS | 9 | L  | Din<6>  | Qout<6>  | CE  | Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D  | CCLK  | CLR  | EXP8_.EXP
INPUTMC | 4 | 3 | 12 | 2 | 13 | 2 | 15 | 3 | 11
INPUTP | 5 | 58 | 71 | 67 | 87 | 50
IMPORTS | 1 | 3 | 11
EQ | 11 | 
   Qout<6>.D = L & Din<6>
	# Qout<6> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
;Imported pterms FB4_12
	# !CE & !L & 
	Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D;
   Qout<6>.CLK = CCLK;
   Qout<6>.AR = CLR;

MACROCELL | 1 | 2 | Temp<7>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 1 | 2 | 1 | 5 | 1 | 12
INPUTS | 9 | L  | Din<7>  | Qout<7>  | CE  | Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D  | CCLK  | CLR  | EXP3_.EXP
INPUTMC | 4 | 1 | 2 | 2 | 11 | 1 | 12 | 1 | 1
INPUTP | 5 | 58 | 46 | 67 | 87 | 50
IMPORTS | 1 | 1 | 1
EQ | 11 | 
   Qout<7>.D = L & Din<7>
	# Qout<7> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
;Imported pterms FB2_2
	# !CE & !L & 
	Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D;
   Qout<7>.CLK = CCLK;
   Qout<7>.AR = CLR;

MACROCELL | 1 | 7 | Temp<8>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 1 | 7 | 1 | 4 | 1 | 11
INPUTS | 9 | L  | Din<8>  | Qout<8>  | CE  | Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D  | CCLK  | CLR  | Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2.EXP
INPUTMC | 4 | 1 | 7 | 1 | 5 | 1 | 11 | 1 | 6
INPUTP | 5 | 58 | 38 | 67 | 87 | 50
IMPORTS | 1 | 1 | 6
EQ | 11 | 
   Qout<8>.D = L & Din<8>
	# Qout<8> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
;Imported pterms FB2_7
	# !CE & !L & 
	Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D;
   Qout<8>.CLK = CCLK;
   Qout<8>.AR = CLR;

MACROCELL | 1 | 13 | Temp<9>
ATTRIBUTES | 8782640 | 0
OUTPUTMC | 3 | 1 | 13 | 1 | 3 | 1 | 10
INPUTS | 9 | L  | Din<9>  | Qout<9>  | CE  | Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D  | CCLK  | CLR  | Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D.EXP
INPUTMC | 4 | 1 | 13 | 1 | 4 | 1 | 10 | 1 | 12
INPUTP | 5 | 58 | 11 | 67 | 87 | 50
IMPORTS | 1 | 1 | 12
EQ | 11 | 
   Qout<9>.D = L & Din<9>
	# Qout<9> & CE & !L
	# !CE & !L & 
	!Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
;Imported pterms FB2_13
	# !CE & !L & 
	Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D;
   Qout<9>.CLK = CCLK;
   Qout<9>.AR = CLR;

MACROCELL | 0 | 7 | Temp<12>
ATTRIBUTES | 4588336 | 0
OUTPUTMC | 2 | 0 | 7 | 0 | 6
INPUTS | 10 | Qout<11>  | UP  | CE  | L  | Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2  | Qout<12>  | Din<12>  | CCLK  | CLR  | EXP1_.EXP
INPUTMC | 4 | 0 | 2 | 1 | 17 | 0 | 7 | 0 | 6
INPUTP | 6 | 9 | 67 | 58 | 26 | 87 | 50
IMPORTS | 1 | 0 | 6
EQ | 9 | 
   Qout<12>.T = !Qout<12> & L & Din<12>
	# Qout<11> & UP & !CE & !L & 
	Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
	# !Qout<11> & !UP & !CE & !L & 
	!Temp_Maddsub__n0000__n0067<0>/Temp_Maddsub__n0000__n0067<0>_D2
;Imported pterms FB1_7
	# Qout<12> & L & !Din<12>;
   Qout<12>.CLK = CCLK;
   Qout<12>.AR = CLR;

MACROCELL | 1 | 3 | Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 2 | 2 | 2 | 1 | 17
INPUTS | 3 | Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D  | Qout<9>
INPUTMC | 3 | 1 | 4 | 1 | 10 | 1 | 13
EQ | 5 | 
   Temp_Maddsub__n0000__n0065<0>/Temp_Maddsub__n0000__n0065<0>_D2 = Qout<9> & 
	!Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<9>__n0002<0>_D;

MACROCELL | 1 | 4 | Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 1 | 13 | 1 | 3 | 1 | 12
INPUTS | 3 | Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D  | Qout<8>
INPUTMC | 3 | 1 | 5 | 1 | 11 | 1 | 7
EQ | 5 | 
   Temp_Maddsub__n0000__n0063<0>/Temp_Maddsub__n0000__n0063<0>_D2 = Qout<8> & 
	!Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<8>__n0002<0>_D;

MACROCELL | 1 | 5 | Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 1 | 7 | 1 | 4 | 1 | 6
INPUTS | 3 | Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D  | Qout<7>
INPUTMC | 3 | 2 | 11 | 1 | 12 | 1 | 2
EQ | 5 | 
   Temp_Maddsub__n0000__n0061<0>/Temp_Maddsub__n0000__n0061<0>_D2 = Qout<7> & 
	!Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<7>__n0002<0>_D;

MACROCELL | 2 | 11 | Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 1 | 2 | 1 | 5 | 1 | 1 | 2 | 12
INPUTS | 7 | Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D  | Qout<6>  | CE  | L  | Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2  | Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D
INPUTMC | 5 | 2 | 13 | 2 | 15 | 3 | 12 | 1 | 6 | 2 | 17
INPUTP | 2 | 67 | 58
EXPORTS | 1 | 2 | 12
EQ | 8 | 
   Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2 = Qout<6> & 
	!Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D
	# 
	Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2 & 
	Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<6>__n0002<0>_D;
    Temp_Maddsub__n0000__n0059<0>/Temp_Maddsub__n0000__n0059<0>_D2.EXP  =  !CE & !L & 
	Temp_Maddsub__n0000__n0053<0>/Temp_Maddsub__n0000__n0053<0>_D2 & 
	!Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>/Temp_Maddsub__n0000_Mxor_Result<4>__n0002<0>_D

MACROCELL | 2 | 13 | Temp_Maddsub__n0000__n0057<0>/Temp_Maddsub__n0000__n0057<0>_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 3 | 3 | 12 | 2 | 11 | 3 | 11