📄 dq24.rpt
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DQ8 2 0 0 3 FB2_14 STD 9 I/O O
(unused) 0 0 0 5 FB2_15 11 I/O I
(unused) 0 0 0 5 FB2_16 10 I/O
DQ4 2 0 0 3 FB2_17 STD 12 I/O O
(unused) 0 0 0 5 FB2_18 92 I/O
Signals Used by Logic in Function Block
1: DQ4_OBUF.FBK.LFBK 6: DQ9_OBUF.FBK.LFBK 10: Din<6>
2: DQ5_OBUF.FBK.LFBK 7: D 11: Din<7>
3: DQ6_OBUF.FBK.LFBK 8: Din<4> 12: Din<8>
4: DQ7_OBUF.FBK.LFBK 9: Din<5> 13: Din<9>
5: DQ8_OBUF.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ9 .....XX.....X........................... 3 3
DQ5 .X....X.X............................... 3 3
DQ6 ..X...X..X.............................. 3 3
DQ7 ...X..X...X............................. 3 3
DQ8 ....X.X....X............................ 3 3
DQ4 X.....XX................................ 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 13/23
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
DQ0 2 0 0 3 FB3_1 STD 41 I/O O
(unused) 0 0 0 5 FB3_2 32 I/O I
(unused) 0 0 0 5 FB3_3 49 I/O
DQ11 2 0 0 3 FB3_4 STD 50 I/O O
(unused) 0 0 0 5 FB3_5 35 I/O I
(unused) 0 0 0 5 FB3_6 53 I/O
DQ13 2 0 0 3 FB3_7 STD 54 I/O O
(unused) 0 0 0 5 FB3_8 37 I/O I
(unused) 0 0 0 5 FB3_9 42 I/O I
DQ14 2 0 0 3 FB3_10 STD 60 I/O O
(unused) 0 0 0 5 FB3_11 52 I/O I
(unused) 0 0 0 5 FB3_12 61 I/O
DQ15 2 0 0 3 FB3_13 STD 63 I/O O
(unused) 0 0 0 5 FB3_14 55 I/O I
(unused) 0 0 0 5 FB3_15 56 I/O I
DQ16 2 0 0 3 FB3_16 STD 65 I/O O
(unused) 0 0 0 5 FB3_17 58 I/O I
(unused) 0 0 0 5 FB3_18 59 I/O
Signals Used by Logic in Function Block
1: DQ0_OBUF.FBK.LFBK 6: DQ16_OBUF.FBK.LFBK
10: Din<13>
2: DQ11_OBUF.FBK.LFBK
7: D 11: Din<14>
3: DQ13_OBUF.FBK.LFBK
8: Din<0> 12: Din<15>
4: DQ14_OBUF.FBK.LFBK
9: Din<11> 13: Din<16>
5: DQ15_OBUF.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ0 X.....XX................................ 3 3
DQ11 .X....X.X............................... 3 3
DQ13 ..X...X..X.............................. 3 3
DQ14 ...X..X...X............................. 3 3
DQ15 ....X.X....X............................ 3 3
DQ16 .....XX.....X........................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 13/23
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
DQ10 2 0 0 3 FB4_1 STD 66 I/O O
(unused) 0 0 0 5 FB4_2 64 I/O I
(unused) 0 0 0 5 FB4_3 71 I/O
DQ12 2 0 0 3 FB4_4 STD 72 I/O O
(unused) 0 0 0 5 FB4_5 67 I/O I
(unused) 0 0 0 5 FB4_6 76 I/O
DQ22 2 0 0 3 FB4_7 STD 77 I/O O
(unused) 0 0 0 5 FB4_8 68 I/O I
(unused) 0 0 0 5 FB4_9 70 I/O I
DQ23 2 0 0 3 FB4_10 STD 81 I/O O
(unused) 0 0 0 5 FB4_11 74 I/O I
(unused) 0 0 0 5 FB4_12 82 I/O
DQ2 2 0 0 3 FB4_13 STD 85 I/O O
(unused) 0 0 0 5 FB4_14 78 I/O I
(unused) 0 0 0 5 FB4_15 89 I/O I
DQ3 2 0 0 3 FB4_16 STD 86 I/O O
(unused) 0 0 0 5 FB4_17 90 I/O I
(unused) 0 0 0 5 FB4_18 79 I/O
Signals Used by Logic in Function Block
1: DQ10_OBUF.FBK.LFBK
6: DQ3_OBUF.FBK.LFBK 10: Din<22>
2: DQ12_OBUF.FBK.LFBK
7: D 11: Din<23>
3: DQ22_OBUF.FBK.LFBK
8: Din<10> 12: Din<2>
4: DQ23_OBUF.FBK.LFBK
9: Din<12> 13: Din<3>
5: DQ2_OBUF.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ10 X.....XX................................ 3 3
DQ12 .X....X.X............................... 3 3
DQ22 ..X...X..X.............................. 3 3
DQ23 ...X..X...X............................. 3 3
DQ2 ....X.X....X............................ 3 3
DQ3 .....XX.....X........................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
FDCPE_DQ0: FDCPE port map (DQ0,DQ0_D,WR,REST,'0');
DQ0_D <= ((D AND Din(0))
OR (NOT Din(0) AND DQ0_OBUF.FBK.LFBK));
FDCPE_DQ10: FDCPE port map (DQ10,DQ10_D,WR,REST,'0');
DQ10_D <= ((D AND Din(10))
OR (NOT Din(10) AND DQ10_OBUF.FBK.LFBK));
FDCPE_DQ11: FDCPE port map (DQ11,DQ11_D,WR,REST,'0');
DQ11_D <= ((D AND Din(11))
OR (NOT Din(11) AND DQ11_OBUF.FBK.LFBK));
FDCPE_DQ12: FDCPE port map (DQ12,DQ12_D,WR,REST,'0');
DQ12_D <= ((D AND Din(12))
OR (NOT Din(12) AND DQ12_OBUF.FBK.LFBK));
FDCPE_DQ13: FDCPE port map (DQ13,DQ13_D,WR,REST,'0');
DQ13_D <= ((D AND Din(13))
OR (NOT Din(13) AND DQ13_OBUF.FBK.LFBK));
FDCPE_DQ14: FDCPE port map (DQ14,DQ14_D,WR,REST,'0');
DQ14_D <= ((D AND Din(14))
OR (NOT Din(14) AND DQ14_OBUF.FBK.LFBK));
FDCPE_DQ15: FDCPE port map (DQ15,DQ15_D,WR,REST,'0');
DQ15_D <= ((D AND Din(15))
OR (NOT Din(15) AND DQ15_OBUF.FBK.LFBK));
FDCPE_DQ16: FDCPE port map (DQ16,DQ16_D,WR,REST,'0');
DQ16_D <= ((D AND Din(16))
OR (NOT Din(16) AND DQ16_OBUF.FBK.LFBK));
FDCPE_DQ17: FDCPE port map (DQ17,DQ17_D,WR,REST,'0');
DQ17_D <= ((D AND Din(17))
OR (NOT Din(17) AND DQ17_OBUF.FBK.LFBK));
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