📄 dq24.rpt
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cpldfit: version G.35 Xilinx Inc.
Fitter Report
Design Name: dq24 Date: 4- 5-2006, 4:02PM
Device Used: XC9572-10-TQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
24 /72 ( 33%) 48 /360 ( 13%) 24 /72 ( 33%) 51 /72 ( 71%) 52 /144 ( 36%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 25 25 | I/O : 49 17
Output : 24 24 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 1 1 |
---- ----
Total 51 51
MACROCELL RESOURCES:
Total Macrocells Available 72
Registered Macrocells 24
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
Signal 'WR' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Signal 'REST' mapped onto global set/reset net GSR.
POWER DATA:
There are 24 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 24 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
DQ0 2 3 FB3_1 STD FAST 41 I/O O RESET
DQ1 2 3 FB1_7 STD FAST 25 I/O O RESET
DQ10 2 3 FB4_1 STD FAST 66 I/O O RESET
DQ11 2 3 FB3_4 STD FAST 50 I/O O RESET
DQ12 2 3 FB4_4 STD FAST 72 I/O O RESET
DQ13 2 3 FB3_7 STD FAST 54 I/O O RESET
DQ14 2 3 FB3_10 STD FAST 60 I/O O RESET
DQ15 2 3 FB3_13 STD FAST 63 I/O O RESET
DQ16 2 3 FB3_16 STD FAST 65 I/O O RESET
DQ17 2 3 FB1_13 STD FAST 36 I/O O RESET
DQ18 2 3 FB1_1 STD FAST 16 I/O O RESET
DQ19 2 3 FB1_4 STD FAST 20 I/O O RESET
DQ2 2 3 FB4_13 STD FAST 85 I/O O RESET
DQ20 2 3 FB1_10 STD FAST 28 I/O O RESET
DQ21 2 3 FB1_16 STD FAST 39 I/O O RESET
DQ22 2 3 FB4_7 STD FAST 77 I/O O RESET
DQ23 2 3 FB4_10 STD FAST 81 I/O O RESET
DQ3 2 3 FB4_16 STD FAST 86 I/O O RESET
DQ4 2 3 FB2_17 STD FAST 12 I/O O RESET
DQ5 2 3 FB2_5 STD FAST 95 I/O O RESET
DQ6 2 3 FB2_8 STD FAST 97 I/O O RESET
DQ7 2 3 FB2_10 STD FAST 1 I/O O RESET
DQ8 2 3 FB2_14 STD FAST 9 I/O O RESET
DQ9 2 3 FB2_2 STD FAST 94 I/O O RESET
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
D FB3_2 32 I/O I
Din<0> FB4_15 89 I/O I
Din<10> FB1_17 30 I/O I
Din<11> FB4_5 67 I/O I
Din<12> FB4_9 70 I/O I
Din<13> FB3_5 35 I/O I
Din<14> FB4_14 78 I/O I
Din<15> FB2_6 96 I/O I
Din<16> FB3_17 58 I/O I
Din<17> FB3_15 56 I/O I
Din<18> FB4_2 64 I/O I
Din<19> FB2_15 11 I/O I
Din<1> FB4_11 74 I/O I
Din<20> FB1_8 17 I/O I
Din<21> FB1_15 29 I/O I
Din<22> FB1_6 15 I/O I
Din<23> FB3_14 55 I/O I
Din<2> FB3_8 37 I/O I
Din<3> FB2_3 91 I/O I
Din<4> FB1_2 13 I/O I
Din<5> FB1_5 14 I/O I
Din<6> FB4_17 90 I/O I
Din<7> FB3_11 52 I/O I
Din<8> FB3_9 42 I/O I
Din<9> FB4_8 68 I/O I
REST FB2_9 99 GSR/I/O GSR
WR FB1_9 22 GCK/I/O GCK
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 6 13 13 12 6/0 18
FB2 6 13 13 12 6/0 18
FB3 6 13 13 12 6/0 18
FB4 6 13 13 12 6/0 18
---- ----- ----- -----
24 48 24/0 72
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 13/23
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
DQ18 2 0 0 3 FB1_1 STD 16 I/O O
(unused) 0 0 0 5 FB1_2 13 I/O I
(unused) 0 0 0 5 FB1_3 18 I/O
DQ19 2 0 0 3 FB1_4 STD 20 I/O O
(unused) 0 0 0 5 FB1_5 14 I/O I
(unused) 0 0 0 5 FB1_6 15 I/O I
DQ1 2 0 0 3 FB1_7 STD 25 I/O O
(unused) 0 0 0 5 FB1_8 17 I/O I
(unused) 0 0 0 5 FB1_9 22 GCK/I/O GCK
DQ20 2 0 0 3 FB1_10 STD 28 I/O O
(unused) 0 0 0 5 FB1_11 23 GCK/I/O
(unused) 0 0 0 5 FB1_12 33 I/O
DQ17 2 0 0 3 FB1_13 STD 36 I/O O
(unused) 0 0 0 5 FB1_14 27 GCK/I/O
(unused) 0 0 0 5 FB1_15 29 I/O I
DQ21 2 0 0 3 FB1_16 STD 39 I/O O
(unused) 0 0 0 5 FB1_17 30 I/O I
(unused) 0 0 0 5 FB1_18 40 I/O
Signals Used by Logic in Function Block
1: DQ17_OBUF.FBK.LFBK
6: DQ21_OBUF.FBK.LFBK
10: Din<19>
2: DQ18_OBUF.FBK.LFBK
7: D 11: Din<1>
3: DQ19_OBUF.FBK.LFBK
8: Din<17> 12: Din<20>
4: DQ1_OBUF.FBK.LFBK 9: Din<18> 13: Din<21>
5: DQ20_OBUF.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
DQ18 .X....X.X............................... 3 3
DQ19 ..X...X..X.............................. 3 3
DQ1 ...X..X...X............................. 3 3
DQ20 ....X.X....X............................ 3 3
DQ17 X.....XX................................ 3 3
DQ21 .....XX.....X........................... 3 3
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 13/23
Number of signals used by logic mapping into function block: 13
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 87 I/O
DQ9 2 0 0 3 FB2_2 STD 94 I/O O
(unused) 0 0 0 5 FB2_3 91 I/O I
(unused) 0 0 0 5 FB2_4 93 I/O
DQ5 2 0 0 3 FB2_5 STD 95 I/O O
(unused) 0 0 0 5 FB2_6 96 I/O I
(unused) 0 0 0 5 FB2_7 3 GTS/I/O
DQ6 2 0 0 3 FB2_8 STD 97 I/O O
(unused) 0 0 0 5 FB2_9 99 GSR/I/O GSR
DQ7 2 0 0 3 FB2_10 STD 1 I/O O
(unused) 0 0 0 5 FB2_11 4 GTS/I/O
(unused) 0 0 0 5 FB2_12 6 I/O
(unused) 0 0 0 5 FB2_13 8 I/O
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