d24wave.ant

xilinx xc9572 cpld 实现的伺服电机控制器

			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ16(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ16,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ16);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ17(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ17,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ17);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ18(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ18,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ18);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ19(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ19,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ19);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ20(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ20,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ20);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ21(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ21,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ21);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ22(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ22,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ22);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_DQ23(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",DQ23,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, DQ23);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CHECK_LOOP : LOOP
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		ANNOTATE_DQ3(TX_TIME);
		ANNOTATE_DQ1(TX_TIME);
		ANNOTATE_DQ2(TX_TIME);
		ANNOTATE_DQ4(TX_TIME);
		ANNOTATE_DQ5(TX_TIME);
		ANNOTATE_DQ6(TX_TIME);
		ANNOTATE_DQ7(TX_TIME);
		ANNOTATE_DQ8(TX_TIME);
		ANNOTATE_DQ0(TX_TIME);
		ANNOTATE_DQ9(TX_TIME);
		ANNOTATE_DQ10(TX_TIME);
		ANNOTATE_DQ11(TX_TIME);
		ANNOTATE_DQ12(TX_TIME);
		ANNOTATE_DQ13(TX_TIME);
		ANNOTATE_DQ14(TX_TIME);
		ANNOTATE_DQ15(TX_TIME);
		ANNOTATE_DQ16(TX_TIME);
		ANNOTATE_DQ17(TX_TIME);
		ANNOTATE_DQ18(TX_TIME);
		ANNOTATE_DQ19(TX_TIME);
		ANNOTATE_DQ20(TX_TIME);
		ANNOTATE_DQ21(TX_TIME);
		ANNOTATE_DQ22(TX_TIME);
		ANNOTATE_DQ23(TX_TIME);
		WAIT FOR 50 ns;
		TX_TIME := TX_TIME + 50;
		END LOOP CHECK_LOOP;
	END PROCESS;

	PROCESS
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000000"); --0
		REST <= transport '0';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		REST <= transport '0';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		REST <= transport '0';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		Din <= transport std_logic_vector'("000000000000000000000001"); --1
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		Din <= transport std_logic_vector'("000000000000000000000010"); --2
		REST <= transport '1';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		REST <= transport '1';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1100 ns
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		REST <= transport '1';
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1200 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1300 ns
		Din <= transport std_logic_vector'("000000000000000000000100"); --4
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1400 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		REST <= transport '1';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1500 ns
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1600 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		Din <= transport std_logic_vector'("000000000000000000001000"); --8
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1800 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1900 ns
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2000 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2100 ns
		Din <= transport std_logic_vector'("000000000000000000010000"); --10
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2200 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2300 ns
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2400 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2500 ns
		Din <= transport std_logic_vector'("000000000000000000100000"); --20
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2600 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2700 ns
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2800 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=2900 ns
		Din <= transport std_logic_vector'("000000000000000001000000"); --40
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3000 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3100 ns
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3200 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3300 ns
		Din <= transport std_logic_vector'("000000000000000010000000"); --80
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3400 ns
		D <= transport '1';
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3500 ns
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3600 ns
		D <= transport '0';
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3700 ns
		Din <= transport std_logic_vector'("000000000000000100000000"); --100
		WR <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=3800 ns
		D <= transport '1';
		WR <= transport '0';
		-- --------------------
		WAIT FOR 700 ns; -- Time=4500 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION dq24_cfg OF d24wave IS
	FOR testbench_arch
	END FOR;
END dq24_cfg;