mdecode.gyd

xilinx xc9572 cpld 实现的伺服电机控制器

Pin Freeze File:  version G.35

9572100TQ XC9572-10-TQ100
CLR0 S:PIN68
CLR1 S:PIN14
MA0 S:PIN11
MA1 S:PIN95
MB0 S:PIN74
MB1 S:PIN56
MC0 S:PIN17
MC1 S:PIN29
RD S:PIN97
O<0> S:PIN32
O<1> S:PIN64
O<2> S:PIN94
O<3> S:PIN6
O<4> S:PIN60
O<5> S:PIN13
O<6> S:PIN81
O<7> S:PIN28


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_2 O_5
PARTITION FB1_8 Q4<2>/Q4<2>_CLKF__$INT Q41<2>/Q41<2>_CLKF__$INT O_7 Q4<3>
		 Q4<2> Q4<1> Q4<0> Q41<3>
		 Q41<2> Q41<1> Q41<0>
PARTITION FB2_2 O_2
PARTITION FB2_12 O_3

PARTITION FB3_2 O_0
PARTITION FB3_10 O_4

PARTITION FB4_2 O_1
PARTITION FB4_10 O_6