mdecode.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : xil_2752_10
-- /___/   /\     Timestamp : 04/04/2006 15:24:15
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: mdecode
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity mdecode is
   port (  MA0    : in    std_logic; 
           MB0    : in    std_logic; 
           MC0    : in    std_logic; 
           MA1    : in    std_logic; 
           MB1    : in    std_logic; 
           MC1    : in    std_logic; 
			  CLR0   : in    std_logic;
			  CLR1   : in    std_logic;
			  RD     : in    std_logic; 
           O      : out   std_logic_vector (7 downto 0)); 
   end mdecode;

architecture BEHAVIORAL of mdecode is
	COMPONENT count4
	PORT(
		CE : IN std_logic;
		CLR : IN std_logic;
		UP : IN std_logic_vector(1 downto 0);
		CCLK : IN std_logic;          
		Qout : OUT std_logic_vector(3 downto 0)
		);
	END COMPONENT;
  signal temp0:   std_logic_vector (1 downto 0);
  signal temp1:   std_logic_vector (1 downto 0);
  signal  Q4:    std_logic_vector (3 downto 0);
  signal  Q41:   std_logic_vector(3 downto 0);
  signal clk0:   std_logic;
  signal clk1:   std_logic;
begin
 
  clk0<=not (MA0 AND MB0 AND (not MC0));
  clk1<=not (MA1 AND MB1 AND (not MC1));	 
 temp0(1 downto 0)<=MB0 & MA0;
 temp1(1 downto 0)<=MB1 & MA1;
 Inst_counter8: count4 PORT MAP(
		CE =>'0',
		CLR => CLR0,
		UP(1 downto 0)  =>temp0(1 downto 0),
		CCLK =>clk0,
		Qout(3 downto 0) =>Q4(3 downto 0) 
	);
 Inst1_counter8: count4 PORT MAP(
		CE =>'0',
		CLR => CLR1,
		UP(1 downto 0) => temp1(1 downto 0),
		CCLK =>clk1,
		Qout(3 downto 0) =>Q41(3 downto 0) 
	);

-- O<=Q41 & Q4;
process(RD,Q4,Q41)
 begin
 if(RD='0') then
  O<=Q41 & Q4;
 end if;
 end process;

end BEHAVIORAL;