mdecode_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

      I0 => O_7_D1,
      I1 => O_7_D2,
      O => O_7_D
    );
  O_7_D1_172 : X_ZERO
    port map (
      O => O_7_D1
    );
  O_7_D2_173 : X_ZERO
    port map (
      O => O_7_D2
    );
  O_7_CLKF_174 : X_ZERO
    port map (
      O => O_7_CLKF
    );
  O_7_SETF_175 : X_AND2
    port map (
      I0 => Q41_3_FBK,
      I1 => NlwInverterSignal_O_7_SETF_IN1,
      O => O_7_SETF
    );
  O_7_RSTF_176 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_7_RSTF_IN0,
      I1 => NlwInverterSignal_O_7_RSTF_IN1,
      O => O_7_RSTF
    );
  Q41_2_Q41_2_CLKF_INT_FBK_177 : X_BUF
    port map (
      I => Q41_2_Q41_2_CLKF_INT_Q,
      O => Q41_2_Q41_2_CLKF_INT_FBK
    );
  Q41_2_Q41_2_CLKF_INT_Q_178 : X_BUF
    port map (
      I => Q41_2_Q41_2_CLKF_INT_D,
      O => Q41_2_Q41_2_CLKF_INT_Q
    );
  Q41_2_Q41_2_CLKF_INT_D_179 : X_XOR2
    port map (
      I0 => Q41_2_Q41_2_CLKF_INT_D1,
      I1 => Q41_2_Q41_2_CLKF_INT_D2,
      O => Q41_2_Q41_2_CLKF_INT_D
    );
  Q41_2_Q41_2_CLKF_INT_D1_180 : X_ZERO
    port map (
      O => Q41_2_Q41_2_CLKF_INT_D1
    );
  Q41_2_Q41_2_CLKF_INT_D2_181 : X_AND3
    port map (
      I0 => MA1_IBUF,
      I1 => MB1_IBUF,
      I2 => NlwInverterSignal_Q41_2_Q41_2_CLKF_INT_D2_IN2,
      O => Q41_2_Q41_2_CLKF_INT_D2
    );
  Q4_2_Q4_2_CLKF_INT_FBK_182 : X_BUF
    port map (
      I => Q4_2_Q4_2_CLKF_INT_Q,
      O => Q4_2_Q4_2_CLKF_INT_FBK
    );
  Q4_2_Q4_2_CLKF_INT_Q_183 : X_BUF
    port map (
      I => Q4_2_Q4_2_CLKF_INT_D,
      O => Q4_2_Q4_2_CLKF_INT_Q
    );
  Q4_2_Q4_2_CLKF_INT_D_184 : X_XOR2
    port map (
      I0 => Q4_2_Q4_2_CLKF_INT_D1,
      I1 => Q4_2_Q4_2_CLKF_INT_D2,
      O => Q4_2_Q4_2_CLKF_INT_D
    );
  Q4_2_Q4_2_CLKF_INT_D1_185 : X_ZERO
    port map (
      O => Q4_2_Q4_2_CLKF_INT_D1
    );
  Q4_2_Q4_2_CLKF_INT_D2_186 : X_AND3
    port map (
      I0 => MA0_IBUF,
      I1 => MB0_IBUF,
      I2 => NlwInverterSignal_Q4_2_Q4_2_CLKF_INT_D2_IN2,
      O => Q4_2_Q4_2_CLKF_INT_D2
    );
  NlwInverterBlock_Q41_0_D2_PT_0_IN1 : X_INV
    port map (
      I => MB1_IBUF,
      O => NlwInverterSignal_Q41_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Q41_0_D2_PT_1_IN0 : X_INV
    port map (
      I => MA1_IBUF,
      O => NlwInverterSignal_Q41_0_D2_PT_1_IN0
    );
  NlwInverterBlock_Q41_0_CLKF_IN0 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_0_CLKF_IN0
    );
  NlwInverterBlock_Q41_0_CLKF_IN1 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_0_CLKF_IN1
    );
  NlwInverterBlock_Q4_0_D2_PT_0_IN1 : X_INV
    port map (
      I => MB0_IBUF,
      O => NlwInverterSignal_Q4_0_D2_PT_0_IN1
    );
  NlwInverterBlock_Q4_0_D2_PT_1_IN0 : X_INV
    port map (
      I => MA0_IBUF,
      O => NlwInverterSignal_Q4_0_D2_PT_1_IN0
    );
  NlwInverterBlock_Q4_0_CLKF_IN0 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_0_CLKF_IN0
    );
  NlwInverterBlock_Q4_0_CLKF_IN1 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_0_CLKF_IN1
    );
  NlwInverterBlock_Q41_1_D2_PT_0_IN1 : X_INV
    port map (
      I => MB1_IBUF,
      O => NlwInverterSignal_Q41_1_D2_PT_0_IN1
    );
  NlwInverterBlock_Q41_1_D2_PT_1_IN0 : X_INV
    port map (
      I => MA1_IBUF,
      O => NlwInverterSignal_Q41_1_D2_PT_1_IN0
    );
  NlwInverterBlock_Q41_1_D2_PT_1_IN2 : X_INV
    port map (
      I => Q41_0_FBK,
      O => NlwInverterSignal_Q41_1_D2_PT_1_IN2
    );
  NlwInverterBlock_Q41_1_CLKF_IN0 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_1_CLKF_IN0
    );
  NlwInverterBlock_Q41_1_CLKF_IN1 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_1_CLKF_IN1
    );
  NlwInverterBlock_Q4_1_D2_PT_0_IN1 : X_INV
    port map (
      I => MB0_IBUF,
      O => NlwInverterSignal_Q4_1_D2_PT_0_IN1
    );
  NlwInverterBlock_Q4_1_D2_PT_1_IN0 : X_INV
    port map (
      I => MA0_IBUF,
      O => NlwInverterSignal_Q4_1_D2_PT_1_IN0
    );
  NlwInverterBlock_Q4_1_D2_PT_1_IN2 : X_INV
    port map (
      I => Q4_0_FBK,
      O => NlwInverterSignal_Q4_1_D2_PT_1_IN2
    );
  NlwInverterBlock_Q4_1_CLKF_IN0 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_1_CLKF_IN0
    );
  NlwInverterBlock_Q4_1_CLKF_IN1 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_1_CLKF_IN1
    );
  NlwInverterBlock_Q41_2_D2_PT_0_IN1 : X_INV
    port map (
      I => MB1_IBUF,
      O => NlwInverterSignal_Q41_2_D2_PT_0_IN1
    );
  NlwInverterBlock_Q41_2_D2_PT_1_IN0 : X_INV
    port map (
      I => MA1_IBUF,
      O => NlwInverterSignal_Q41_2_D2_PT_1_IN0
    );
  NlwInverterBlock_Q41_2_D2_PT_1_IN2 : X_INV
    port map (
      I => Q41_0_FBK,
      O => NlwInverterSignal_Q41_2_D2_PT_1_IN2
    );
  NlwInverterBlock_Q41_2_D2_PT_1_IN3 : X_INV
    port map (
      I => Q41_1_FBK,
      O => NlwInverterSignal_Q41_2_D2_PT_1_IN3
    );
  NlwInverterBlock_Q41_2_CLKF_IN0 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_2_CLKF_IN0
    );
  NlwInverterBlock_Q41_2_CLKF_IN1 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_2_CLKF_IN1
    );
  NlwInverterBlock_Q4_2_D2_PT_0_IN1 : X_INV
    port map (
      I => MB0_IBUF,
      O => NlwInverterSignal_Q4_2_D2_PT_0_IN1
    );
  NlwInverterBlock_Q4_2_D2_PT_1_IN0 : X_INV
    port map (
      I => MA0_IBUF,
      O => NlwInverterSignal_Q4_2_D2_PT_1_IN0
    );
  NlwInverterBlock_Q4_2_D2_PT_1_IN2 : X_INV
    port map (
      I => Q4_0_FBK,
      O => NlwInverterSignal_Q4_2_D2_PT_1_IN2
    );
  NlwInverterBlock_Q4_2_D2_PT_1_IN3 : X_INV
    port map (
      I => Q4_1_FBK,
      O => NlwInverterSignal_Q4_2_D2_PT_1_IN3
    );
  NlwInverterBlock_Q4_2_CLKF_IN0 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_2_CLKF_IN0
    );
  NlwInverterBlock_Q4_2_CLKF_IN1 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_2_CLKF_IN1
    );
  NlwInverterBlock_Q41_3_D2_PT_0_IN1 : X_INV
    port map (
      I => MB1_IBUF,
      O => NlwInverterSignal_Q41_3_D2_PT_0_IN1
    );
  NlwInverterBlock_Q41_3_D2_PT_1_IN0 : X_INV
    port map (
      I => MA1_IBUF,
      O => NlwInverterSignal_Q41_3_D2_PT_1_IN0
    );
  NlwInverterBlock_Q41_3_D2_PT_1_IN2 : X_INV
    port map (
      I => Q41_3_FBK,
      O => NlwInverterSignal_Q41_3_D2_PT_1_IN2
    );
  NlwInverterBlock_Q41_3_CLKF_IN0 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_3_CLKF_IN0
    );
  NlwInverterBlock_Q41_3_CLKF_IN1 : X_INV
    port map (
      I => Q41_2_Q41_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q41_3_CLKF_IN1
    );
  NlwInverterBlock_Q4_3_D2_PT_0_IN1 : X_INV
    port map (
      I => MB0_IBUF,
      O => NlwInverterSignal_Q4_3_D2_PT_0_IN1
    );
  NlwInverterBlock_Q4_3_D2_PT_1_IN0 : X_INV
    port map (
      I => MA0_IBUF,
      O => NlwInverterSignal_Q4_3_D2_PT_1_IN0
    );
  NlwInverterBlock_Q4_3_D2_PT_1_IN2 : X_INV
    port map (
      I => Q4_3_FBK,
      O => NlwInverterSignal_Q4_3_D2_PT_1_IN2
    );
  NlwInverterBlock_Q4_3_CLKF_IN0 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_3_CLKF_IN0
    );
  NlwInverterBlock_Q4_3_CLKF_IN1 : X_INV
    port map (
      I => Q4_2_Q4_2_CLKF_INT_FBK,
      O => NlwInverterSignal_Q4_3_CLKF_IN1
    );
  NlwInverterBlock_O_0_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_0_RSTF,
      O => NlwInverterSignal_O_0_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_0_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_0_SETF_IN1
    );
  NlwInverterBlock_O_0_RSTF_IN0 : X_INV
    port map (
      I => Q4(0),
      O => NlwInverterSignal_O_0_RSTF_IN0
    );
  NlwInverterBlock_O_0_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_0_RSTF_IN1
    );
  NlwInverterBlock_O_1_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_1_RSTF,
      O => NlwInverterSignal_O_1_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_1_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_1_SETF_IN1
    );
  NlwInverterBlock_O_1_RSTF_IN0 : X_INV
    port map (
      I => Q4(1),
      O => NlwInverterSignal_O_1_RSTF_IN0
    );
  NlwInverterBlock_O_1_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_1_RSTF_IN1
    );
  NlwInverterBlock_O_2_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_2_RSTF,
      O => NlwInverterSignal_O_2_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_2_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_2_SETF_IN1
    );
  NlwInverterBlock_O_2_RSTF_IN0 : X_INV
    port map (
      I => Q4(2),
      O => NlwInverterSignal_O_2_RSTF_IN0
    );
  NlwInverterBlock_O_2_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_2_RSTF_IN1
    );
  NlwInverterBlock_O_3_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_3_RSTF,
      O => NlwInverterSignal_O_3_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_3_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_3_SETF_IN1
    );
  NlwInverterBlock_O_3_RSTF_IN0 : X_INV
    port map (
      I => Q4(3),
      O => NlwInverterSignal_O_3_RSTF_IN0
    );
  NlwInverterBlock_O_3_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_3_RSTF_IN1
    );
  NlwInverterBlock_O_4_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_4_RSTF,
      O => NlwInverterSignal_O_4_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_4_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_4_SETF_IN1
    );
  NlwInverterBlock_O_4_RSTF_IN0 : X_INV
    port map (
      I => Q41_0_Q_0,
      O => NlwInverterSignal_O_4_RSTF_IN0
    );
  NlwInverterBlock_O_4_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_4_RSTF_IN1
    );
  NlwInverterBlock_O_5_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_5_RSTF,
      O => NlwInverterSignal_O_5_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_5_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_5_SETF_IN1
    );
  NlwInverterBlock_O_5_RSTF_IN0 : X_INV
    port map (
      I => Q41_1_FBK,
      O => NlwInverterSignal_O_5_RSTF_IN0
    );
  NlwInverterBlock_O_5_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_5_RSTF_IN1
    );
  NlwInverterBlock_O_6_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_6_RSTF,
      O => NlwInverterSignal_O_6_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_6_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_6_SETF_IN1
    );
  NlwInverterBlock_O_6_RSTF_IN0 : X_INV
    port map (
      I => Q41_2_Q_1,
      O => NlwInverterSignal_O_6_RSTF_IN0
    );
  NlwInverterBlock_O_6_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_6_RSTF_IN1
    );
  NlwInverterBlock_O_7_tsimcreated_set_and_noreset_IN0 : X_INV
    port map (
      I => O_7_RSTF,
      O => NlwInverterSignal_O_7_tsimcreated_set_and_noreset_IN0
    );
  NlwInverterBlock_O_7_SETF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_7_SETF_IN1
    );
  NlwInverterBlock_O_7_RSTF_IN0 : X_INV
    port map (
      I => Q41_3_FBK,
      O => NlwInverterSignal_O_7_RSTF_IN0
    );
  NlwInverterBlock_O_7_RSTF_IN1 : X_INV
    port map (
      I => RD_IBUF,
      O => NlwInverterSignal_O_7_RSTF_IN1
    );
  NlwInverterBlock_Q41_2_Q41_2_CLKF_INT_D2_IN2 : X_INV
    port map (
      I => MC1_IBUF,
      O => NlwInverterSignal_Q41_2_Q41_2_CLKF_INT_D2_IN2
    );
  NlwInverterBlock_Q4_2_Q4_2_CLKF_INT_D2_IN2 : X_INV
    port map (
      I => MC0_IBUF,
      O => NlwInverterSignal_Q4_2_Q4_2_CLKF_INT_D2_IN2
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => PRLD);

end Structure;