mdecode_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

      I0 => Q4_3_D1,
      I1 => Q4_3_D2,
      O => Q4_3_D
    );
  Q4_3_D1_99 : X_ZERO
    port map (
      O => Q4_3_D1
    );
  Q4_3_D2_PT_0_100 : X_AND3
    port map (
      I0 => MA0_IBUF,
      I1 => NlwInverterSignal_Q4_3_D2_PT_0_IN1,
      I2 => Q4_3_FBK,
      O => Q4_3_D2_PT_0
    );
  Q4_3_D2_PT_1_101 : X_AND3
    port map (
      I0 => NlwInverterSignal_Q4_3_D2_PT_1_IN0,
      I1 => MB0_IBUF,
      I2 => NlwInverterSignal_Q4_3_D2_PT_1_IN2,
      O => Q4_3_D2_PT_1
    );
  Q4_3_D2_102 : X_OR2
    port map (
      I0 => Q4_3_D2_PT_0,
      I1 => Q4_3_D2_PT_1,
      O => Q4_3_D2
    );
  Q4_3_CLKF_103 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q4_3_CLKF_IN0,
      I1 => NlwInverterSignal_Q4_3_CLKF_IN1,
      O => Q4_3_CLKF
    );
  Q4_3_RSTF_104 : X_AND2
    port map (
      I0 => CLR0_IBUF,
      I1 => CLR0_IBUF,
      O => Q4_3_RSTF
    );
  O_0_105 : X_BUF
    port map (
      I => O_0_Q,
      O => O_0
    );
  O_0_tsimcreated_set_and_noreset_Q_106 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_0_tsimcreated_set_and_noreset_IN0,
      I1 => O_0_SETF,
      O => O_0_tsimcreated_set_and_noreset_Q
    );
  O_0_tsimcreated_prld_Q_107 : X_OR2
    port map (
      I0 => O_0_RSTF,
      I1 => PRLD,
      O => O_0_tsimcreated_prld_Q
    );
  O_0_REG : X_FF
    port map (
      I => O_0_D,
      CE => Vcc,
      CLK => O_0_CLKF,
      SET => O_0_tsimcreated_set_and_noreset_Q,
      RST => O_0_tsimcreated_prld_Q,
      O => O_0_Q
    );
  O_0_D_108 : X_XOR2
    port map (
      I0 => O_0_D1,
      I1 => O_0_D2,
      O => O_0_D
    );
  O_0_D1_109 : X_ZERO
    port map (
      O => O_0_D1
    );
  O_0_D2_110 : X_ZERO
    port map (
      O => O_0_D2
    );
  O_0_CLKF_111 : X_ZERO
    port map (
      O => O_0_CLKF
    );
  O_0_SETF_112 : X_AND2
    port map (
      I0 => Q4(0),
      I1 => NlwInverterSignal_O_0_SETF_IN1,
      O => O_0_SETF
    );
  O_0_RSTF_113 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_0_RSTF_IN0,
      I1 => NlwInverterSignal_O_0_RSTF_IN1,
      O => O_0_RSTF
    );
  O_1_114 : X_BUF
    port map (
      I => O_1_Q,
      O => O_1
    );
  O_1_tsimcreated_set_and_noreset_Q_115 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_1_tsimcreated_set_and_noreset_IN0,
      I1 => O_1_SETF,
      O => O_1_tsimcreated_set_and_noreset_Q
    );
  O_1_tsimcreated_prld_Q_116 : X_OR2
    port map (
      I0 => O_1_RSTF,
      I1 => PRLD,
      O => O_1_tsimcreated_prld_Q
    );
  O_1_REG : X_FF
    port map (
      I => O_1_D,
      CE => Vcc,
      CLK => O_1_CLKF,
      SET => O_1_tsimcreated_set_and_noreset_Q,
      RST => O_1_tsimcreated_prld_Q,
      O => O_1_Q
    );
  O_1_D_117 : X_XOR2
    port map (
      I0 => O_1_D1,
      I1 => O_1_D2,
      O => O_1_D
    );
  O_1_D1_118 : X_ZERO
    port map (
      O => O_1_D1
    );
  O_1_D2_119 : X_ZERO
    port map (
      O => O_1_D2
    );
  O_1_CLKF_120 : X_ZERO
    port map (
      O => O_1_CLKF
    );
  O_1_SETF_121 : X_AND2
    port map (
      I0 => Q4(1),
      I1 => NlwInverterSignal_O_1_SETF_IN1,
      O => O_1_SETF
    );
  O_1_RSTF_122 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_1_RSTF_IN0,
      I1 => NlwInverterSignal_O_1_RSTF_IN1,
      O => O_1_RSTF
    );
  O_2_123 : X_BUF
    port map (
      I => O_2_Q,
      O => O_2
    );
  O_2_tsimcreated_set_and_noreset_Q_124 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_2_tsimcreated_set_and_noreset_IN0,
      I1 => O_2_SETF,
      O => O_2_tsimcreated_set_and_noreset_Q
    );
  O_2_tsimcreated_prld_Q_125 : X_OR2
    port map (
      I0 => O_2_RSTF,
      I1 => PRLD,
      O => O_2_tsimcreated_prld_Q
    );
  O_2_REG : X_FF
    port map (
      I => O_2_D,
      CE => Vcc,
      CLK => O_2_CLKF,
      SET => O_2_tsimcreated_set_and_noreset_Q,
      RST => O_2_tsimcreated_prld_Q,
      O => O_2_Q
    );
  O_2_D_126 : X_XOR2
    port map (
      I0 => O_2_D1,
      I1 => O_2_D2,
      O => O_2_D
    );
  O_2_D1_127 : X_ZERO
    port map (
      O => O_2_D1
    );
  O_2_D2_128 : X_ZERO
    port map (
      O => O_2_D2
    );
  O_2_CLKF_129 : X_ZERO
    port map (
      O => O_2_CLKF
    );
  O_2_SETF_130 : X_AND2
    port map (
      I0 => Q4(2),
      I1 => NlwInverterSignal_O_2_SETF_IN1,
      O => O_2_SETF
    );
  O_2_RSTF_131 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_2_RSTF_IN0,
      I1 => NlwInverterSignal_O_2_RSTF_IN1,
      O => O_2_RSTF
    );
  O_3_132 : X_BUF
    port map (
      I => O_3_Q,
      O => O_3
    );
  O_3_tsimcreated_set_and_noreset_Q_133 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_3_tsimcreated_set_and_noreset_IN0,
      I1 => O_3_SETF,
      O => O_3_tsimcreated_set_and_noreset_Q
    );
  O_3_tsimcreated_prld_Q_134 : X_OR2
    port map (
      I0 => O_3_RSTF,
      I1 => PRLD,
      O => O_3_tsimcreated_prld_Q
    );
  O_3_REG : X_FF
    port map (
      I => O_3_D,
      CE => Vcc,
      CLK => O_3_CLKF,
      SET => O_3_tsimcreated_set_and_noreset_Q,
      RST => O_3_tsimcreated_prld_Q,
      O => O_3_Q
    );
  O_3_D_135 : X_XOR2
    port map (
      I0 => O_3_D1,
      I1 => O_3_D2,
      O => O_3_D
    );
  O_3_D1_136 : X_ZERO
    port map (
      O => O_3_D1
    );
  O_3_D2_137 : X_ZERO
    port map (
      O => O_3_D2
    );
  O_3_CLKF_138 : X_ZERO
    port map (
      O => O_3_CLKF
    );
  O_3_SETF_139 : X_AND2
    port map (
      I0 => Q4(3),
      I1 => NlwInverterSignal_O_3_SETF_IN1,
      O => O_3_SETF
    );
  O_3_RSTF_140 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_3_RSTF_IN0,
      I1 => NlwInverterSignal_O_3_RSTF_IN1,
      O => O_3_RSTF
    );
  O_4_141 : X_BUF
    port map (
      I => O_4_Q,
      O => O_4
    );
  O_4_tsimcreated_set_and_noreset_Q_142 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_4_tsimcreated_set_and_noreset_IN0,
      I1 => O_4_SETF,
      O => O_4_tsimcreated_set_and_noreset_Q
    );
  O_4_tsimcreated_prld_Q_143 : X_OR2
    port map (
      I0 => O_4_RSTF,
      I1 => PRLD,
      O => O_4_tsimcreated_prld_Q
    );
  O_4_REG : X_FF
    port map (
      I => O_4_D,
      CE => Vcc,
      CLK => O_4_CLKF,
      SET => O_4_tsimcreated_set_and_noreset_Q,
      RST => O_4_tsimcreated_prld_Q,
      O => O_4_Q
    );
  O_4_D_144 : X_XOR2
    port map (
      I0 => O_4_D1,
      I1 => O_4_D2,
      O => O_4_D
    );
  O_4_D1_145 : X_ZERO
    port map (
      O => O_4_D1
    );
  O_4_D2_146 : X_ZERO
    port map (
      O => O_4_D2
    );
  O_4_CLKF_147 : X_ZERO
    port map (
      O => O_4_CLKF
    );
  O_4_SETF_148 : X_AND2
    port map (
      I0 => Q41_0_Q_0,
      I1 => NlwInverterSignal_O_4_SETF_IN1,
      O => O_4_SETF
    );
  O_4_RSTF_149 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_4_RSTF_IN0,
      I1 => NlwInverterSignal_O_4_RSTF_IN1,
      O => O_4_RSTF
    );
  O_5_150 : X_BUF
    port map (
      I => O_5_Q,
      O => O_5
    );
  O_5_tsimcreated_set_and_noreset_Q_151 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_5_tsimcreated_set_and_noreset_IN0,
      I1 => O_5_SETF,
      O => O_5_tsimcreated_set_and_noreset_Q
    );
  O_5_tsimcreated_prld_Q_152 : X_OR2
    port map (
      I0 => O_5_RSTF,
      I1 => PRLD,
      O => O_5_tsimcreated_prld_Q
    );
  O_5_REG : X_FF
    port map (
      I => O_5_D,
      CE => Vcc,
      CLK => O_5_CLKF,
      SET => O_5_tsimcreated_set_and_noreset_Q,
      RST => O_5_tsimcreated_prld_Q,
      O => O_5_Q
    );
  O_5_D_153 : X_XOR2
    port map (
      I0 => O_5_D1,
      I1 => O_5_D2,
      O => O_5_D
    );
  O_5_D1_154 : X_ZERO
    port map (
      O => O_5_D1
    );
  O_5_D2_155 : X_ZERO
    port map (
      O => O_5_D2
    );
  O_5_CLKF_156 : X_ZERO
    port map (
      O => O_5_CLKF
    );
  O_5_SETF_157 : X_AND2
    port map (
      I0 => Q41_1_FBK,
      I1 => NlwInverterSignal_O_5_SETF_IN1,
      O => O_5_SETF
    );
  O_5_RSTF_158 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_5_RSTF_IN0,
      I1 => NlwInverterSignal_O_5_RSTF_IN1,
      O => O_5_RSTF
    );
  O_6_159 : X_BUF
    port map (
      I => O_6_Q,
      O => O_6
    );
  O_6_tsimcreated_set_and_noreset_Q_160 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_6_tsimcreated_set_and_noreset_IN0,
      I1 => O_6_SETF,
      O => O_6_tsimcreated_set_and_noreset_Q
    );
  O_6_tsimcreated_prld_Q_161 : X_OR2
    port map (
      I0 => O_6_RSTF,
      I1 => PRLD,
      O => O_6_tsimcreated_prld_Q
    );
  O_6_REG : X_FF
    port map (
      I => O_6_D,
      CE => Vcc,
      CLK => O_6_CLKF,
      SET => O_6_tsimcreated_set_and_noreset_Q,
      RST => O_6_tsimcreated_prld_Q,
      O => O_6_Q
    );
  O_6_D_162 : X_XOR2
    port map (
      I0 => O_6_D1,
      I1 => O_6_D2,
      O => O_6_D
    );
  O_6_D1_163 : X_ZERO
    port map (
      O => O_6_D1
    );
  O_6_D2_164 : X_ZERO
    port map (
      O => O_6_D2
    );
  O_6_CLKF_165 : X_ZERO
    port map (
      O => O_6_CLKF
    );
  O_6_SETF_166 : X_AND2
    port map (
      I0 => Q41_2_Q_1,
      I1 => NlwInverterSignal_O_6_SETF_IN1,
      O => O_6_SETF
    );
  O_6_RSTF_167 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_6_RSTF_IN0,
      I1 => NlwInverterSignal_O_6_RSTF_IN1,
      O => O_6_RSTF
    );
  O_7_168 : X_BUF
    port map (
      I => O_7_Q,
      O => O_7
    );
  O_7_tsimcreated_set_and_noreset_Q_169 : X_AND2
    port map (
      I0 => NlwInverterSignal_O_7_tsimcreated_set_and_noreset_IN0,
      I1 => O_7_SETF,
      O => O_7_tsimcreated_set_and_noreset_Q
    );
  O_7_tsimcreated_prld_Q_170 : X_OR2
    port map (
      I0 => O_7_RSTF,
      I1 => PRLD,
      O => O_7_tsimcreated_prld_Q
    );
  O_7_REG : X_FF
    port map (
      I => O_7_D,
      CE => Vcc,
      CLK => O_7_CLKF,
      SET => O_7_tsimcreated_set_and_noreset_Q,
      RST => O_7_tsimcreated_prld_Q,
      O => O_7_Q
    );
  O_7_D_171 : X_XOR2
    port map (