mdecode_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

    );
  Q41_0_RSTF_31 : X_AND2
    port map (
      I0 => CLR1_IBUF,
      I1 => CLR1_IBUF,
      O => Q41_0_RSTF
    );
  Q4_0_Q_32 : X_BUF
    port map (
      I => Q4_0_Q,
      O => Q4(0)
    );
  Q4_0_FBK_33 : X_BUF
    port map (
      I => Q4_0_Q,
      O => Q4_0_FBK
    );
  Q4_0_tsimcreated_xor_Q_34 : X_XOR2
    port map (
      I0 => Q4_0_D,
      I1 => Q4_0_Q,
      O => Q4_0_tsimcreated_xor_Q
    );
  Q4_0_tsimcreated_prld_Q_35 : X_OR2
    port map (
      I0 => Q4_0_RSTF,
      I1 => PRLD,
      O => Q4_0_tsimcreated_prld_Q
    );
  Q4_0_REG : X_FF
    port map (
      I => Q4_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q4_0_CLKF,
      SET => Gnd,
      RST => Q4_0_tsimcreated_prld_Q,
      O => Q4_0_Q
    );
  Q4_0_D_36 : X_XOR2
    port map (
      I0 => Q4_0_D1,
      I1 => Q4_0_D2,
      O => Q4_0_D
    );
  Q4_0_D1_37 : X_ZERO
    port map (
      O => Q4_0_D1
    );
  Q4_0_D2_PT_0_38 : X_AND2
    port map (
      I0 => MA0_IBUF,
      I1 => NlwInverterSignal_Q4_0_D2_PT_0_IN1,
      O => Q4_0_D2_PT_0
    );
  Q4_0_D2_PT_1_39 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q4_0_D2_PT_1_IN0,
      I1 => MB0_IBUF,
      O => Q4_0_D2_PT_1
    );
  Q4_0_D2_40 : X_OR2
    port map (
      I0 => Q4_0_D2_PT_0,
      I1 => Q4_0_D2_PT_1,
      O => Q4_0_D2
    );
  Q4_0_CLKF_41 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q4_0_CLKF_IN0,
      I1 => NlwInverterSignal_Q4_0_CLKF_IN1,
      O => Q4_0_CLKF
    );
  Q4_0_RSTF_42 : X_AND2
    port map (
      I0 => CLR0_IBUF,
      I1 => CLR0_IBUF,
      O => Q4_0_RSTF
    );
  Q41_1_FBK_43 : X_BUF
    port map (
      I => Q41_1_Q,
      O => Q41_1_FBK
    );
  Q41_1_tsimcreated_xor_Q_44 : X_XOR2
    port map (
      I0 => Q41_1_D,
      I1 => Q41_1_Q,
      O => Q41_1_tsimcreated_xor_Q
    );
  Q41_1_tsimcreated_prld_Q_45 : X_OR2
    port map (
      I0 => Q41_1_RSTF,
      I1 => PRLD,
      O => Q41_1_tsimcreated_prld_Q
    );
  Q41_1_REG : X_FF
    port map (
      I => Q41_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q41_1_CLKF,
      SET => Gnd,
      RST => Q41_1_tsimcreated_prld_Q,
      O => Q41_1_Q
    );
  Q41_1_D_46 : X_XOR2
    port map (
      I0 => Q41_1_D1,
      I1 => Q41_1_D2,
      O => Q41_1_D
    );
  Q41_1_D1_47 : X_ZERO
    port map (
      O => Q41_1_D1
    );
  Q41_1_D2_PT_0_48 : X_AND3
    port map (
      I0 => MA1_IBUF,
      I1 => NlwInverterSignal_Q41_1_D2_PT_0_IN1,
      I2 => Q41_0_FBK,
      O => Q41_1_D2_PT_0
    );
  Q41_1_D2_PT_1_49 : X_AND3
    port map (
      I0 => NlwInverterSignal_Q41_1_D2_PT_1_IN0,
      I1 => MB1_IBUF,
      I2 => NlwInverterSignal_Q41_1_D2_PT_1_IN2,
      O => Q41_1_D2_PT_1
    );
  Q41_1_D2_50 : X_OR2
    port map (
      I0 => Q41_1_D2_PT_0,
      I1 => Q41_1_D2_PT_1,
      O => Q41_1_D2
    );
  Q41_1_CLKF_51 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q41_1_CLKF_IN0,
      I1 => NlwInverterSignal_Q41_1_CLKF_IN1,
      O => Q41_1_CLKF
    );
  Q41_1_RSTF_52 : X_AND2
    port map (
      I0 => CLR1_IBUF,
      I1 => CLR1_IBUF,
      O => Q41_1_RSTF
    );
  Q4_1_Q_53 : X_BUF
    port map (
      I => Q4_1_Q,
      O => Q4(1)
    );
  Q4_1_FBK_54 : X_BUF
    port map (
      I => Q4_1_Q,
      O => Q4_1_FBK
    );
  Q4_1_tsimcreated_xor_Q_55 : X_XOR2
    port map (
      I0 => Q4_1_D,
      I1 => Q4_1_Q,
      O => Q4_1_tsimcreated_xor_Q
    );
  Q4_1_tsimcreated_prld_Q_56 : X_OR2
    port map (
      I0 => Q4_1_RSTF,
      I1 => PRLD,
      O => Q4_1_tsimcreated_prld_Q
    );
  Q4_1_REG : X_FF
    port map (
      I => Q4_1_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q4_1_CLKF,
      SET => Gnd,
      RST => Q4_1_tsimcreated_prld_Q,
      O => Q4_1_Q
    );
  Q4_1_D_57 : X_XOR2
    port map (
      I0 => Q4_1_D1,
      I1 => Q4_1_D2,
      O => Q4_1_D
    );
  Q4_1_D1_58 : X_ZERO
    port map (
      O => Q4_1_D1
    );
  Q4_1_D2_PT_0_59 : X_AND3
    port map (
      I0 => MA0_IBUF,
      I1 => NlwInverterSignal_Q4_1_D2_PT_0_IN1,
      I2 => Q4_0_FBK,
      O => Q4_1_D2_PT_0
    );
  Q4_1_D2_PT_1_60 : X_AND3
    port map (
      I0 => NlwInverterSignal_Q4_1_D2_PT_1_IN0,
      I1 => MB0_IBUF,
      I2 => NlwInverterSignal_Q4_1_D2_PT_1_IN2,
      O => Q4_1_D2_PT_1
    );
  Q4_1_D2_61 : X_OR2
    port map (
      I0 => Q4_1_D2_PT_0,
      I1 => Q4_1_D2_PT_1,
      O => Q4_1_D2
    );
  Q4_1_CLKF_62 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q4_1_CLKF_IN0,
      I1 => NlwInverterSignal_Q4_1_CLKF_IN1,
      O => Q4_1_CLKF
    );
  Q4_1_RSTF_63 : X_AND2
    port map (
      I0 => CLR0_IBUF,
      I1 => CLR0_IBUF,
      O => Q4_1_RSTF
    );
  Q41_2_Q_64 : X_BUF
    port map (
      I => Q41_2_Q,
      O => Q41_2_Q_1
    );
  Q41_2_tsimcreated_xor_Q_65 : X_XOR2
    port map (
      I0 => Q41_2_D,
      I1 => Q41_2_Q,
      O => Q41_2_tsimcreated_xor_Q
    );
  Q41_2_tsimcreated_prld_Q_66 : X_OR2
    port map (
      I0 => Q41_2_RSTF,
      I1 => PRLD,
      O => Q41_2_tsimcreated_prld_Q
    );
  Q41_2_REG : X_FF
    port map (
      I => Q41_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q41_2_CLKF,
      SET => Gnd,
      RST => Q41_2_tsimcreated_prld_Q,
      O => Q41_2_Q
    );
  Q41_2_D_67 : X_XOR2
    port map (
      I0 => Q41_2_D1,
      I1 => Q41_2_D2,
      O => Q41_2_D
    );
  Q41_2_D1_68 : X_ZERO
    port map (
      O => Q41_2_D1
    );
  Q41_2_D2_PT_0_69 : X_AND4
    port map (
      I0 => MA1_IBUF,
      I1 => NlwInverterSignal_Q41_2_D2_PT_0_IN1,
      I2 => Q41_0_FBK,
      I3 => Q41_1_FBK,
      O => Q41_2_D2_PT_0
    );
  Q41_2_D2_PT_1_70 : X_AND4
    port map (
      I0 => NlwInverterSignal_Q41_2_D2_PT_1_IN0,
      I1 => MB1_IBUF,
      I2 => NlwInverterSignal_Q41_2_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Q41_2_D2_PT_1_IN3,
      O => Q41_2_D2_PT_1
    );
  Q41_2_D2_71 : X_OR2
    port map (
      I0 => Q41_2_D2_PT_0,
      I1 => Q41_2_D2_PT_1,
      O => Q41_2_D2
    );
  Q41_2_CLKF_72 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q41_2_CLKF_IN0,
      I1 => NlwInverterSignal_Q41_2_CLKF_IN1,
      O => Q41_2_CLKF
    );
  Q41_2_RSTF_73 : X_AND2
    port map (
      I0 => CLR1_IBUF,
      I1 => CLR1_IBUF,
      O => Q41_2_RSTF
    );
  Q4_2_Q_74 : X_BUF
    port map (
      I => Q4_2_Q,
      O => Q4(2)
    );
  Q4_2_tsimcreated_xor_Q_75 : X_XOR2
    port map (
      I0 => Q4_2_D,
      I1 => Q4_2_Q,
      O => Q4_2_tsimcreated_xor_Q
    );
  Q4_2_tsimcreated_prld_Q_76 : X_OR2
    port map (
      I0 => Q4_2_RSTF,
      I1 => PRLD,
      O => Q4_2_tsimcreated_prld_Q
    );
  Q4_2_REG : X_FF
    port map (
      I => Q4_2_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q4_2_CLKF,
      SET => Gnd,
      RST => Q4_2_tsimcreated_prld_Q,
      O => Q4_2_Q
    );
  Q4_2_D_77 : X_XOR2
    port map (
      I0 => Q4_2_D1,
      I1 => Q4_2_D2,
      O => Q4_2_D
    );
  Q4_2_D1_78 : X_ZERO
    port map (
      O => Q4_2_D1
    );
  Q4_2_D2_PT_0_79 : X_AND4
    port map (
      I0 => MA0_IBUF,
      I1 => NlwInverterSignal_Q4_2_D2_PT_0_IN1,
      I2 => Q4_0_FBK,
      I3 => Q4_1_FBK,
      O => Q4_2_D2_PT_0
    );
  Q4_2_D2_PT_1_80 : X_AND4
    port map (
      I0 => NlwInverterSignal_Q4_2_D2_PT_1_IN0,
      I1 => MB0_IBUF,
      I2 => NlwInverterSignal_Q4_2_D2_PT_1_IN2,
      I3 => NlwInverterSignal_Q4_2_D2_PT_1_IN3,
      O => Q4_2_D2_PT_1
    );
  Q4_2_D2_81 : X_OR2
    port map (
      I0 => Q4_2_D2_PT_0,
      I1 => Q4_2_D2_PT_1,
      O => Q4_2_D2
    );
  Q4_2_CLKF_82 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q4_2_CLKF_IN0,
      I1 => NlwInverterSignal_Q4_2_CLKF_IN1,
      O => Q4_2_CLKF
    );
  Q4_2_RSTF_83 : X_AND2
    port map (
      I0 => CLR0_IBUF,
      I1 => CLR0_IBUF,
      O => Q4_2_RSTF
    );
  Q41_3_FBK_84 : X_BUF
    port map (
      I => Q41_3_Q,
      O => Q41_3_FBK
    );
  Q41_3_tsimcreated_xor_Q_85 : X_XOR2
    port map (
      I0 => Q41_3_D,
      I1 => Q41_3_Q,
      O => Q41_3_tsimcreated_xor_Q
    );
  Q41_3_tsimcreated_prld_Q_86 : X_OR2
    port map (
      I0 => Q41_3_RSTF,
      I1 => PRLD,
      O => Q41_3_tsimcreated_prld_Q
    );
  Q41_3_REG : X_FF
    port map (
      I => Q41_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q41_3_CLKF,
      SET => Gnd,
      RST => Q41_3_tsimcreated_prld_Q,
      O => Q41_3_Q
    );
  Q41_3_D_87 : X_XOR2
    port map (
      I0 => Q41_3_D1,
      I1 => Q41_3_D2,
      O => Q41_3_D
    );
  Q41_3_D1_88 : X_ZERO
    port map (
      O => Q41_3_D1
    );
  Q41_3_D2_PT_0_89 : X_AND3
    port map (
      I0 => MA1_IBUF,
      I1 => NlwInverterSignal_Q41_3_D2_PT_0_IN1,
      I2 => Q41_3_FBK,
      O => Q41_3_D2_PT_0
    );
  Q41_3_D2_PT_1_90 : X_AND3
    port map (
      I0 => NlwInverterSignal_Q41_3_D2_PT_1_IN0,
      I1 => MB1_IBUF,
      I2 => NlwInverterSignal_Q41_3_D2_PT_1_IN2,
      O => Q41_3_D2_PT_1
    );
  Q41_3_D2_91 : X_OR2
    port map (
      I0 => Q41_3_D2_PT_0,
      I1 => Q41_3_D2_PT_1,
      O => Q41_3_D2
    );
  Q41_3_CLKF_92 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q41_3_CLKF_IN0,
      I1 => NlwInverterSignal_Q41_3_CLKF_IN1,
      O => Q41_3_CLKF
    );
  Q41_3_RSTF_93 : X_AND2
    port map (
      I0 => CLR1_IBUF,
      I1 => CLR1_IBUF,
      O => Q41_3_RSTF
    );
  Q4_3_Q_94 : X_BUF
    port map (
      I => Q4_3_Q,
      O => Q4(3)
    );
  Q4_3_FBK_95 : X_BUF
    port map (
      I => Q4_3_Q,
      O => Q4_3_FBK
    );
  Q4_3_tsimcreated_xor_Q_96 : X_XOR2
    port map (
      I0 => Q4_3_D,
      I1 => Q4_3_Q,
      O => Q4_3_tsimcreated_xor_Q
    );
  Q4_3_tsimcreated_prld_Q_97 : X_OR2
    port map (
      I0 => Q4_3_RSTF,
      I1 => PRLD,
      O => Q4_3_tsimcreated_prld_Q
    );
  Q4_3_REG : X_FF
    port map (
      I => Q4_3_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q4_3_CLKF,
      SET => Gnd,
      RST => Q4_3_tsimcreated_prld_Q,
      O => Q4_3_Q
    );
  Q4_3_D_98 : X_XOR2
    port map (