sel4_1.gyd

xilinx xc9572 cpld 实现的伺服电机控制器

Pin Freeze File:  version G.35

9572100TQ XC9572-10-TQ100
A0 S:PIN32
A1 S:PIN97
CS S:PIN95
MR_0<0> S:PIN58
MR_0<1> S:PIN55
MR_0<2> S:PIN52
MR_0<3> S:PIN15
MR_0<4> S:PIN61
MR_0<5> S:PIN74
MR_0<6> S:PIN68
MR_0<7> S:PIN67
MR_1<0> S:PIN96
MR_1<1> S:PIN65
MR_1<2> S:PIN42
MR_1<3> S:PIN9
MR_1<4> S:PIN77
MR_1<5> S:PIN11
MR_1<6> S:PIN56
MR_1<7> S:PIN35
MR_2<0> S:PIN30
MR_2<1> S:PIN37
MR_2<2> S:PIN90
MR_2<3> S:PIN94
MR_2<4> S:PIN33
MR_2<5> S:PIN17
MR_2<6> S:PIN14
MR_2<7> S:PIN89
MR_3<0> S:PIN78
MR_3<1> S:PIN16
MR_3<2> S:PIN13
MR_3<3> S:PIN70
MR_3<4> S:PIN50
MR_3<5> S:PIN64
MR_3<6> S:PIN29
MR_3<7> S:PIN12
DO<0> S:PIN49
DO<1> S:PIN71
DO<2> S:PIN91
DO<3> S:PIN60
DO<4> S:PIN81
DO<5> S:PIN18
DO<6> S:PIN28
DO<7> S:PIN6


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_3 DO_5_OBUFE
PARTITION FB1_10 DO_6_OBUFE

PARTITION FB2_3 DO_2_OBUFE
PARTITION FB2_12 DO_7_OBUFE

PARTITION FB3_3 DO_0_OBUFE
PARTITION FB3_10 DO_3_OBUFE

PARTITION FB4_3 DO_1_OBUFE
PARTITION FB4_10 DO_4_OBUFE