top_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

    );
  MA1_IBUF_57 : X_BUF
    port map (
      I => MA1,
      O => MA1_IBUF
    );
  MB1_IBUF_58 : X_BUF
    port map (
      I => MB1,
      O => MB1_IBUF
    );
  MA0_IBUF_59 : X_BUF
    port map (
      I => MA0,
      O => MA0_IBUF
    );
  MB0_IBUF_60 : X_BUF
    port map (
      I => MB0,
      O => MB0_IBUF
    );
  MC0_IBUF_61 : X_BUF
    port map (
      I => MC0,
      O => MC0_IBUF
    );
  MC1_IBUF_62 : X_BUF
    port map (
      I => MC1,
      O => MC1_IBUF
    );
  RD_IBUF_63 : X_BUF
    port map (
      I => RD,
      O => RD_IBUF
    );
  CLK8_IBUF_64 : X_BUF
    port map (
      I => CLK8,
      O => CLK8_IBUF
    );
  INT_L0_IBUF_65 : X_BUF
    port map (
      I => INT_L0,
      O => INT_L0_IBUF
    );
  CS1_66 : X_BUF
    port map (
      I => CS1_OBUF,
      O => CS1
    );
  M1CLR_67 : X_BUF
    port map (
      I => M1CLR_OBUF_Q,
      O => M1CLR
    );
  M1PS_68 : X_BUF
    port map (
      I => M1PS_OBUF_Q,
      O => M1PS
    );
  M1SG_69 : X_BUF
    port map (
      I => M1SG_OBUF_Q,
      O => M1SG
    );
  M2CLR_70 : X_BUF
    port map (
      I => M2CLR_OBUF_Q,
      O => M2CLR
    );
  M2PS_71 : X_BUF
    port map (
      I => M2PS_OBUF_Q,
      O => M2PS
    );
  M2SG_72 : X_BUF
    port map (
      I => M2SG_OBUF_Q,
      O => M2SG
    );
  PC1ON_73 : X_BUF
    port map (
      I => PC1ON_OBUF_Q,
      O => PC1ON
    );
  PC2ON_74 : X_BUF
    port map (
      I => PC2ON_OBUF_Q,
      O => PC2ON
    );
  REL0_75 : X_BUF
    port map (
      I => REL0_OBUF_Q,
      O => REL0
    );
  SEN0_76 : X_BUF
    port map (
      I => SEN0_OBUF_Q,
      O => SEN0
    );
  SEN1_77 : X_BUF
    port map (
      I => SEN1_OBUF_Q,
      O => SEN1
    );
  SEN2_78 : X_BUF
    port map (
      I => SEN2_OBUF_Q,
      O => SEN2
    );
  SPD2A_79 : X_BUF
    port map (
      I => SPD2A_OBUF_Q,
      O => SPD2A
    );
  SPDA1_80 : X_BUF
    port map (
      I => SPDA1_OBUF_Q,
      O => SPDA1
    );
  SPDB1_81 : X_BUF
    port map (
      I => SPDB1_OBUF_Q,
      O => SPDB1
    );
  SPDB2_82 : X_BUF
    port map (
      I => SPDB2_OBUF_Q,
      O => SPDB2
    );
  D_0_Q : X_TRI
    port map (
      I => D_0_IOBUFE,
      CTL => D_0_IOBUFE_OE,
      O => D(0)
    );
  D_1_Q : X_TRI
    port map (
      I => D_1_IOBUFE,
      CTL => D_1_IOBUFE_OE,
      O => D(1)
    );
  D_2_Q : X_TRI
    port map (
      I => D_2_IOBUFE,
      CTL => D_2_IOBUFE_OE,
      O => D(2)
    );
  D_3_Q : X_TRI
    port map (
      I => D_3_IOBUFE,
      CTL => D_3_IOBUFE_OE,
      O => D(3)
    );
  D_4_Q : X_TRI
    port map (
      I => D_4_IOBUFE,
      CTL => D_4_IOBUFE_OE,
      O => D(4)
    );
  D_5_Q : X_TRI
    port map (
      I => D_5_OBUFE,
      CTL => D_5_OBUFE_OE,
      O => D(5)
    );
  D_6_Q : X_TRI
    port map (
      I => D_6_OBUFE,
      CTL => D_6_OBUFE_OE,
      O => D(6)
    );
  D_7_Q : X_TRI
    port map (
      I => D_7_IOBUFE,
      CTL => D_7_IOBUFE_OE,
      O => D(7)
    );
  ALMR_83 : X_BUF
    port map (
      I => ALMR_OBUF,
      O => ALMR
    );
  UART0_84 : X_BUF
    port map (
      I => UART0_OBUF,
      O => UART0
    );
  CLK_85 : X_BUF
    port map (
      I => CLK8_IBUF_BUF0,
      O => CLK
    );
  INT0_86 : X_BUF
    port map (
      I => INT_L0_IBUF_BUF0,
      O => INT0
    );
  CS1_OBUF_87 : X_BUF
    port map (
      I => CS1_OBUF_Q,
      O => CS1_OBUF
    );
  CS1_OBUF_Q_88 : X_BUF
    port map (
      I => CS1_OBUF_D,
      O => CS1_OBUF_Q
    );
  CS1_OBUF_D_89 : X_XOR2
    port map (
      I0 => NlwInverterSignal_CS1_OBUF_D_IN0,
      I1 => CS1_OBUF_D2,
      O => CS1_OBUF_D
    );
  CS1_OBUF_D1_90 : X_ZERO
    port map (
      O => CS1_OBUF_D1
    );
  CS1_OBUF_D2_91 : X_AND4
    port map (
      I0 => NlwInverterSignal_CS1_OBUF_D2_IN0,
      I1 => NlwInverterSignal_CS1_OBUF_D2_IN1,
      I2 => NlwInverterSignal_CS1_OBUF_D2_IN2,
      I3 => NlwInverterSignal_CS1_OBUF_D2_IN3,
      O => CS1_OBUF_D2
    );
  M1CLR_OBUF_Q_92 : X_BUF
    port map (
      I => M1CLR_OBUF_Q_0,
      O => M1CLR_OBUF_Q
    );
  M1CLR_OBUF_FBK_93 : X_BUF
    port map (
      I => M1CLR_OBUF_Q_0,
      O => M1CLR_OBUF_FBK
    );
  M1CLR_OBUF_tsimcreated_xor_Q_94 : X_XOR2
    port map (
      I0 => M1CLR_OBUF_D,
      I1 => M1CLR_OBUF_Q_0,
      O => M1CLR_OBUF_tsimcreated_xor_Q
    );
  M1CLR_OBUF_tsimcreated_prld_Q_95 : X_OR2
    port map (
      I0 => M1CLR_OBUF_RSTF,
      I1 => PRLD,
      O => M1CLR_OBUF_tsimcreated_prld_Q
    );
  M1CLR_OBUF_REG : X_FF
    port map (
      I => M1CLR_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => M1CLR_OBUF_CLKF,
      SET => Gnd,
      RST => M1CLR_OBUF_tsimcreated_prld_Q,
      O => M1CLR_OBUF_Q_0
    );
  Gnd_96 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_97 : X_ONE
    port map (
      O => Vcc
    );
  M1CLR_OBUF_D_98 : X_XOR2
    port map (
      I0 => M1CLR_OBUF_D1,
      I1 => M1CLR_OBUF_D2,
      O => M1CLR_OBUF_D
    );
  M1CLR_OBUF_D1_99 : X_ZERO
    port map (
      O => M1CLR_OBUF_D1
    );
  M1CLR_OBUF_D2_PT_0_100 : X_AND16
    port map (
      I0 => N3927,
      I1 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN1,
      I2 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN2,
      I3 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN3,
      I4 => A1_IBUF,
      I5 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN5,
      I6 => N3937,
      I7 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN7,
      I8 => N3931,
      I9 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN9,
      I10 => NlwInverterSignal_M1CLR_OBUF_D2_PT_0_IN10,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => M1CLR_OBUF_D2_PT_0
    );
  M1CLR_OBUF_D2_PT_1_101 : X_AND16
    port map (
      I0 => N3927,
      I1 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN1,
      I2 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN2,
      I3 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN3,
      I4 => A1_IBUF,
      I5 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN5,
      I6 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN6,
      I7 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN7,
      I8 => N3931,
      I9 => NlwInverterSignal_M1CLR_OBUF_D2_PT_1_IN9,
      I10 => M1CLR_OBUF_FBK,
      I11 => Vcc,
      I12 => Vcc,
      I13 => Vcc,
      I14 => Vcc,
      I15 => Vcc,
      O => M1CLR_OBUF_D2_PT_1
    );
  M1CLR_OBUF_D2_102 : X_OR2
    port map (
      I0 => M1CLR_OBUF_D2_PT_0,
      I1 => M1CLR_OBUF_D2_PT_1,
      O => M1CLR_OBUF_D2
    );
  M1CLR_OBUF_CLKF_103 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => M1CLR_OBUF_CLKF
    );
  M1CLR_OBUF_RSTF_104 : X_AND2
    port map (
      I0 => NlwInverterSignal_M1CLR_OBUF_RSTF_IN0,
      I1 => NlwInverterSignal_M1CLR_OBUF_RSTF_IN1,
      O